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authorSteve Markgraf <steve@steve-m.de>2012-09-19 03:15:43 +0200
committerSteve Markgraf <steve@steve-m.de>2012-09-19 03:15:43 +0200
commita943a2ed257db0c913e81b04486656ce9382b8bd (patch)
tree85c41f3a4353e8218f19d535188af7cbf40c47e3
parent01d8d308fc42ab781d3f32cecb4d2bed3a673b70 (diff)
tuner_fc001x: check if PLL values are within boundaries
This fixes the issue of the FC0013 locking up at frequencies between 928.0 and 950.0 MHz, which happened because the numerator of the fraction exceeded its 5 bit limit. For the tuner to behave normally again, the dongle needed to be replugged. For the FC0013 this now results in a small gap between 948.6 MHz and 950.0 MHz, where no valid PLL values are existant. For the FC0012 tuning is aborted when the maximum frequency has been reached (948.6 MHz). Signed-off-by: Steve Markgraf <steve@steve-m.de>
-rw-r--r--src/tuner_fc0012.c16
-rw-r--r--src/tuner_fc0013.c16
2 files changed, 28 insertions, 4 deletions
diff --git a/src/tuner_fc0012.c b/src/tuner_fc0012.c
index 91ac882..4ad2045 100644
--- a/src/tuner_fc0012.c
+++ b/src/tuner_fc0012.c
@@ -22,6 +22,7 @@
*/
#include <stdint.h>
+#include <stdio.h>
#include "rtlsdr_i2c.h"
#include "tuner_fc0012.h"
@@ -215,12 +216,23 @@ int fc0012_set_params(void *dev, uint32_t freq, uint32_t bandwidth)
am = (uint8_t)(xdiv - (8 * pm));
if (am < 2) {
- reg[1] = am + 8;
- reg[2] = pm - 1;
+ am += 8;
+ pm--;
+ }
+
+ if (pm > 31) {
+ reg[1] = am + (8 * (pm - 31));
+ reg[2] = 31;
} else {
reg[1] = am;
reg[2] = pm;
}
+
+ if (reg[1] > 15) {
+ fprintf(stderr, "[FC0012] no valid PLL combination "
+ "found for %u Hz!\n", freq);
+ return -1;
+ }
} else {
/* fix for frequency less than 45 MHz */
reg[1] = 0x06;
diff --git a/src/tuner_fc0013.c b/src/tuner_fc0013.c
index 5423941..76e4b68 100644
--- a/src/tuner_fc0013.c
+++ b/src/tuner_fc0013.c
@@ -25,6 +25,7 @@
*/
#include <stdint.h>
+#include <stdio.h>
#include "rtlsdr_i2c.h"
#include "tuner_fc0013.h"
@@ -320,12 +321,23 @@ int fc0013_set_params(void *dev, uint32_t freq, uint32_t bandwidth)
am = (uint8_t)(xdiv - (8 * pm));
if (am < 2) {
- reg[1] = am + 8;
- reg[2] = pm - 1;
+ am += 8;
+ pm--;
+ }
+
+ if (pm > 31) {
+ reg[1] = am + (8 * (pm - 31));
+ reg[2] = 31;
} else {
reg[1] = am;
reg[2] = pm;
}
+
+ if (reg[1] > 15) {
+ fprintf(stderr, "[FC0013] no valid PLL combination "
+ "found for %u Hz!\n", freq);
+ return -1;
+ }
} else {
/* fix for frequency less than 45 MHz */
reg[1] = 0x06;