path: root/bts
AgeCommit message (Expand)AuthorFilesLines
2018-03-17bts: Add TC_sacch_multi_chgHarald Welte1-0/+72
2018-03-17bts: Add TC_sacch_multi to test for scheduling of multiple SI on SACCHHarald Welte1-1/+46
2018-03-16ignore results of .ttcnpp filesNeels Hofmeyr1-0/+2
2018-03-16fix don't include source dir as link targetNeels Hofmeyr1-8/+1
2018-03-13bts: Verify the PCU protocol interface versionHarald Welte1-5/+6
2018-03-13remove *.default from [EXECUTE] in *.default filesHarald Welte1-1/+0
2018-03-12bts: Add TC_sacch_info_mod and TC_sacch_fillingHarald Welte1-0/+105
2018-03-12bts: Add f_rsl_transceive() flag to ignore all unrelated messagesHarald Welte1-6/+8
2018-03-12bts: Add TC_deact_sacch()Harald Welte1-0/+91
2018-03-12bts: Add f_shutdown() for clean shutdown; use it from testsHarald Welte1-4/+35
2018-03-12bts: Send DM_REL_REQ to L1 when closing logical channelHarald Welte1-0/+1
2018-03-12bts: f_rsl_transceive: Add altsteps for sacch/facch/meas_repHarald Welte1-0/+3
2018-03-12bts: Make f_TC_meas_res_periodic work with real BTSHarald Welte1-5/+10
2018-03-12bts: Ignore first MEAS REP as it often contains bogus valuesHarald Welte1-2/+12
2018-03-12bts: Introduce RxLev/RxQual tolerance valuesHarald Welte1-4/+43
2018-03-12bts: Make PCU and TRXC sockets optionalHarald Welte1-4/+13
2018-03-12bts: Align default SI contents with what we see from OsmoBSCHarald Welte1-5/+5
2018-03-12BTS_Tests: Access Control Classes are invertedHarald Welte1-1/+1
2018-03-12L1CTL/bts: Fix tons of compiler warnings by splitting rx+tx templatesHarald Welte1-19/+22
2018-03-12bts: Add test for SI1 schedulingHarald Welte1-2/+9
2018-03-12BTS_Tests: Fix SI L2 pseudo-length and rest octetsHarald Welte1-7/+7
2018-03-05bts/BTS_Tests.ttcn: update TC_rach_max_ta test caseVadim Yanitskiy1-1/+3
2018-03-02bts: f_validate_si_scheduling(): Print correct TC valueHarald Welte1-1/+1
2018-03-02f_rach_toffs: Print toffs256 value in verdict when failingHarald Welte1-1/+1
2018-03-01bts: ensure fake_trx BB CTRL IP is used from main componentHarald Welte1-2/+2
2018-03-01bts: Make IP address of fake_trx BB CTRL port configurableHarald Welte1-2/+3
2018-02-28bts: Update towards most recent "laforge/trx" branchHarald Welte1-5/+5
2018-02-28bts: Add PCU Interface testcasesHarald Welte3-0/+419
2018-02-28bts: Fix bugs in RACH Tests (timer not started, wrong CS/PS function)Harald Welte1-3/+3
2018-02-27bts: Add test for high-resulotion timing offset / TOA256Harald Welte1-0/+20
2018-02-27bts: Add TELNET/VTY module so we can interact with BTS VTYHarald Welte4-4/+19
2018-02-27bts: Instruct trxcon for TA=2 at every testcase startHarald Welte1-1/+4
2018-02-27Add new f_timer_safe_restart() function for warning-safe restartHarald Welte1-3/+2
2018-02-27bts: TC_rach_max_taHarald Welte1-0/+64
2018-02-27bts: Add TC_rach_content and TC_rach_countHarald Welte1-11/+86
2018-02-27L1CTL: Add message segmentation helper via getMsgLen()Harald Welte2-2/+2
2018-02-25WIP: bts: SI scheduling testsHarald Welte1-1/+459
2018-02-25bts: Add some more comments for better code groupingHarald Welte1-2/+28
2018-02-25bts: Set not only SI3 but also SI2+SI4 during initializationHarald Welte1-15/+57
2018-02-25Merge duplicate SI3 in GSM_RR_Types and GSM_SystemInformationHarald Welte2-14/+17
2018-02-25bts: Add TC_ipa_crcx_mdcx_mdcx_dlcx_not_active (2x MDCX on lchan)Harald Welte1-0/+28
2018-02-25bts: Add TC_ipa_crcx_sdcch_not_active (CRCX on SDDCH)Harald Welte1-0/+20
2018-02-25bts: Sleep for some time after RSL is up before using itHarald Welte1-0/+1
2018-02-25bts: TC_ipa_crcx_twice_not_active + TC_ipa_crcx_mdcx_dlcx_not_activeHarald Welte1-0/+38
2018-02-25bts: Introduce f_rsl_transceive() and reduce code duplicationHarald Welte1-32/+22
2018-02-25RSL: Make ts_RSL_IPA_DLCX require a conn_id valueHarald Welte1-1/+1
2018-02-25bts: Add TC_ipa_dlcx_not_active()Harald Welte1-0/+24
2018-02-25bts: low-level RSL ERROR REPORT TestingHarald Welte1-2/+53
2018-02-25bts: Add paging related testsHarald Welte2-10/+352
2018-02-25bts: Type Definition + Template for SI3; Send SI3 at start of testHarald Welte1-0/+66