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2019-06-22update PDF schematics and placement to v2ohm4_ocxo_v2Harald Welte2-0/+0
2019-06-22add a power-indicator LED to the NVS board and tag it v2Harald Welte2-41/+451
2019-06-22initial import of osmo-nvs-gps projectHarald Welte5-0/+9316
This is a small eval board for the NVS GPS/GLONASS/GALILEO module, exporting UARTs on headers.
2019-06-22update gerbers...Harald Welte4-664/+681
2019-06-22don't put solder cream on SMA edge pads.Harald Welte2-194/+204
The sma edge connectors are hand soldered after the SMT soldering is already done. We don't want to have solder paste on them...
2019-06-22component placement PDFs bottom and topHarald Welte2-0/+0
2019-06-22re-generate geber (fiducials, labels on soldermask)Harald Welte6-1678/+1803
2019-06-22move fonts on bottom to soldermask layer (no silk screen rqd)Harald Welte1-3/+3
2019-06-22add fiducials for automatic mounting of componentsHarald Welte1-0/+24
2019-06-22Specify LED series resistor as 100 OhmsHarald Welte2-2/+2
2019-06-22mark R1 as 'DNP' (no stub to U.FL connector)Harald Welte2-2/+2
2019-06-22add placement files for top and bottomHarald Welte2-0/+53
2019-06-22import gerber outputHarald Welte10-0/+12173
2019-06-22add CAM file for generating gerber outputHarald Welte1-0/+135
2019-06-22remove D45014F marking (seeedstudio)Harald Welte1-1/+0
2019-06-22update the _brd.pdf to include the LED and R13 and correspond with schemsticsHarald Welte1-0/+0
2019-06-22add updated PDF schematicsHarald Welte1-0/+0
2019-06-22approve various ERC changesHarald Welte2-3/+21
2019-06-22re-merge my previous changes manually into the projectHarald Welte2-24/+25
2019-06-22sylvains branch (ignores some of harald's changes)Harald Welte2-59/+1678
2019-06-22don't have two SERIAL_RXD labels but one RXD and one TXDHarald Welte1-1/+1
2019-06-22add ublox LEA6T evaluation board design, first versionHarald Welte4-0/+13218
2019-06-19Merge branch 'laforge/clock-gen-v2'Harald Welte2-5152/+9533
2019-06-19clock-generator: Move GND via to avoid overlap with N$15Harald Welte1-6/+6
2019-06-19<osmo-clock-gen: add more TVS for exposed signals, clean up and finishMartin Schramm2-536/+1391
2019-06-19osmo-clock-gen: capacitive coupling for XA input needed - added 100nMartin Schramm2-58/+101
This was a remark by tnt, thanks.
2019-06-19clock-generator: compacting + place MTA100 header (solves OSM#4050)Martin Schramm2-1208/+509
2019-06-19clock-generator: changes adressing OSM#4050Martin Schramm2-1831/+2677
A shouded UEXT would need much space; no room for an MTA100 yet... tbd
2019-06-19clock-generator: insert changes discussed so far for v2Martin Schramm2-4207/+7211
* selectable VDDIO{1..4} for PLL: either 3V3 or ADJ (VOUT/DAC) * use SAMD21 instead of SAMD11 * bring some GPIO on pin header * use GCLK_IO4 (PA10) to feed XA of PLL
2019-06-19clock-generator: add tracking LDO, make PCB four layerMartin Schramm2-634/+1045
2019-06-19WIP: click-generator: Replace U3 (so far SAMD11) with SAMD21Harald Welte2-775/+696
Closes: OS#3856
2019-05-09sfp-*: add OSHW logo, fill ext'd attribs for BOMMartin Schramm4-444/+912
2019-05-08sfp: update BOMs for both breakout and experimenter PCBsMartin Schramm2-0/+1059
2019-02-14clock-converter: Export BOMHarald Welte1-0/+591
2019-02-14clock-converter: Add attributes with digikey linksHarald Welte2-106/+1589
2019-02-02Clock converter for low phase noise sine -> square conversionHarald Welte5-0/+5194
2019-01-28clock-gen: Add BOM information + PDF exports of schematicsHarald Welte5-298/+3653
2019-01-27clock-gen: Update gpio spreadsheet with all assignmentsHarald Welte1-30/+73
The assignments have been chosen to be nearly identical to the SAMD11-XPRO board.
2019-01-27Merge branch 'laforge/clock-gen'Harald Welte12-0/+120372
2019-01-27clock-gen: Minor changes; final version as orderedHarald Welte2-40/+52
* move DC jack to extend beyond PCB edge into front panel * harmonize component variants (10n only 0402, 4.7u only 0805) * add "sysmocom" as manufacturer name (WEEE requirement)
2019-01-27clock-gen: Cosmetic changesHarald Welte2-1118/+1177
2019-01-27clock-gen: finish routing of PCB layoutHarald Welte4-442/+1596
2019-01-26clock-gen: Connect EEPROM WP to GND to disable write-protectHarald Welte2-0/+6
2019-01-26clock-gen: Add SPI; UEXT header; mounting holes; do layout/routingHarald Welte3-177/+1042
2019-01-23clock-generator: Most of the layoutHarald Welte2-2093/+2770
Traces are intended for dual-layer 1mm FR4 PCB with 35um copper.
2019-01-23clock-generator: More schematics work; initial placement/groupingHarald Welte2-0/+2366
* add I2C EEPROM * start board design file * group parts to their respective "main part" * define TC-2030 pinout
2019-01-21clock-generator: More work on schematics (USB, UART, ESD)Harald Welte1-57/+868
2019-01-16initial check-in of upcoming clock-generator boardHarald Welte9-0/+114422
2019-01-08SFP: publish experimenter and breakout schematicss as pdfMartin Schramm2-0/+0
2018-10-06add SFP multi-source agreement to give context to the boardsHarald Welte1-0/+0