AgeCommit message (Expand)AuthorFilesLines
2020-01-27support DFU detach to switch from fw to bootloaderlaforge/dfurtEric Wild8-3/+653
2019-12-06WIP: Add DFU runtime descriptorHarald Welte4-4/+133
2019-12-06Implement serial number string descriptor in CTRL EP callbackHarald Welte3-3/+83
2019-12-06change iManufacturer to full sysmocom company nameHarald Welte4-6/+6
2019-12-02reenable host buildsEric Wild1-2/+2
2019-12-02rename the global talloc contextEric Wild3-15/+15
2019-12-02fix the host/emulation buildEric Wild5-19/+32
2019-12-01Check for osmo_fsm_register() error return valueHarald Welte1-4/+4
2019-11-30jenkins.sh: Add --publish to publish binaries, similar to simtrace2.gitHarald Welte1-1/+25
2019-11-28reenable firmware build0.2Eric Wild1-3/+3
2019-11-28prettier slot bitmask codeEric Wild1-2/+2
2019-11-28enable the final slotEric Wild12-264/+353
2019-11-28first attempt at rx timeout handlingEric Wild3-28/+142
2019-11-28cuart cleanupEric Wild1-15/+15
2019-11-28cuart: fix etu calculationEric Wild1-2/+6
2019-11-28cuart: allow getting the icc baud rate and clock freqEric Wild2-0/+12
2019-11-28change uart ctl define namesEric Wild3-6/+6
2019-11-28the magic sauce that makes it workEric Wild1-0/+4
2019-11-28boost uart priorityEric Wild1-0/+6
2019-11-28pps warningEric Wild1-0/+7
2019-11-28add a note for D=64 pecularitiesEric Wild1-0/+8
2019-11-28fsm completion event handling from main loopEric Wild4-21/+68
2019-11-28fix power descriptor valueEric Wild1-1/+2
2019-11-28better ccid error handling, fix buffer leaksEric Wild3-8/+30
2019-11-28add some volatility to debug missing state changesEric Wild1-1/+1
2019-11-28switching rx/tx is too slow, and not necessaryEric Wild1-4/+1
2019-11-28add a "no rx or tx" stateEric Wild3-1/+4
2019-11-28debug code to measure uart timing using the CAN headerEric Wild3-1/+37
2019-11-28debug code to use the DWT unitEric Wild1-0/+23
2019-11-28increase the debug uart buffer sizeEric Wild1-1/+1
2019-11-28attempt at handling card insertion/removalEric Wild6-31/+89
2019-11-28ccid setparameters/PPS supportEric Wild5-21/+322
2019-11-28cuart icc clock freq and divider setting supportEric Wild4-8/+43
2019-11-28move iso7816_3 to common dirEric Wild3-1/+1
2019-11-28prevent uart interrupts before having proper structsEric Wild1-0/+3
2019-11-28no logging, no memory poolEric Wild3-10/+15
2019-11-28talloc assertsEric Wild1-0/+10
2019-11-28increase the uart ring buffer sizeEric Wild1-7/+7
2019-11-28Add card_uart driver for ASF4 USARTHarald Welte6-721/+531
2019-11-28disable build for nowEric Wild1-1/+1
2019-11-28split usb descriptor codeEric Wild4-47/+105
2019-11-28sercom config for t1Eric Wild1-14/+14
2019-11-28don't wait for TCK if card only supports T0Eric Wild1-0/+4
2019-11-13sysmoOCTSIM: Proper Makefile targetsHarald Welte1-7/+18
2019-11-13Makefile: Add 'make mrproper' for removing all bin/elf/etc output filesHarald Welte1-0/+3
2019-11-12Avoid endless loop while printing debug uart ringbufferHarald Welte1-1/+5
2019-11-12Add 'check_ccid_config.py' to test for USB VID/PID in libccid_Info.plistHarald Welte1-0/+60
2019-11-12sysmoOCTSIM: Create symlinks of last-built .bin and .elfHarald Welte1-1/+6
2019-11-12main: Add missing #include to osmocom/timer.hHarald Welte1-0/+1
2019-11-12ccid_device: Fix memory leaks in ccid_handle_out() error pathsHarald Welte1-0/+3