152 lines
6.3 KiB
C
152 lines
6.3 KiB
C
/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.GPL.
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*
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* BSD LICENSE
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*
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* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SCU_CONSTANTS_H_
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#define _SCU_CONSTANTS_H_
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/**
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* This file contains the SCU hardware constants.
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*
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*
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*/
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#include "sci_controller_constants.h"
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/**
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*
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*
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* 2 indicates the maximum number of UFs that can occur for a given IO request.
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* The hardware handles reception of additional unsolicited frames while all
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* UFs are in use, by holding off the transmitting device. This number could
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* be theoretically reduced to 1, but 2 provides for more reliable operation.
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* During SATA PIO operation, it is possible under some conditions for there to
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* be 3 separate FISes received, back to back to back (PIO Setup, Data, D2H
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* Register). It is unlikely to have all 3 pending all at once without some of
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* them already being processed.
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*/
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#define SCU_MIN_UNSOLICITED_FRAMES (1)
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#define SCU_MIN_CRITICAL_NOTIFICATIONS (24)
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#define SCU_MIN_EVENTS (4)
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#define SCU_MIN_COMPLETION_QUEUE_SCRATCH (2)
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#define SCU_MIN_COMPLETION_QUEUE_ENTRIES (SCU_MIN_CRITICAL_NOTIFICATIONS \
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+ SCU_MIN_EVENTS \
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+ SCU_MIN_UNSOLICITED_FRAMES \
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+ SCI_MIN_IO_REQUESTS \
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+ SCU_MIN_COMPLETION_QUEUE_SCRATCH)
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#define SCU_MAX_CRITICAL_NOTIFICATIONS (384)
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#define SCU_MAX_EVENTS (128)
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#define SCU_MAX_UNSOLICITED_FRAMES (128)
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#define SCU_MAX_COMPLETION_QUEUE_SCRATCH (128)
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#define SCU_MAX_COMPLETION_QUEUE_ENTRIES (SCU_MAX_CRITICAL_NOTIFICATIONS \
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+ SCU_MAX_EVENTS \
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+ SCU_MAX_UNSOLICITED_FRAMES \
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+ SCI_MAX_IO_REQUESTS \
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+ SCU_MAX_COMPLETION_QUEUE_SCRATCH)
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#if !defined(ENABLE_MINIMUM_MEMORY_MODE)
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#define SCU_UNSOLICITED_FRAME_COUNT SCU_MAX_UNSOLICITED_FRAMES
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#define SCU_CRITICAL_NOTIFICATION_COUNT SCU_MAX_CRITICAL_NOTIFICATIONS
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#define SCU_EVENT_COUNT SCU_MAX_EVENTS
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#define SCU_COMPLETION_QUEUE_SCRATCH SCU_MAX_COMPLETION_QUEUE_SCRATCH
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#define SCU_IO_REQUEST_COUNT SCI_MAX_IO_REQUESTS
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#define SCU_IO_REQUEST_SGE_COUNT SCI_MAX_SCATTER_GATHER_ELEMENTS
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#define SCU_COMPLETION_QUEUE_COUNT SCU_MAX_COMPLETION_QUEUE_ENTRIES
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#else
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#define SCU_UNSOLICITED_FRAME_COUNT SCU_MIN_UNSOLICITED_FRAMES
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#define SCU_CRITICAL_NOTIFICATION_COUNT SCU_MIN_CRITICAL_NOTIFICATIONS
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#define SCU_EVENT_COUNT SCU_MIN_EVENTS
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#define SCU_COMPLETION_QUEUE_SCRATCH SCU_MIN_COMPLETION_QUEUE_SCRATCH
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#define SCU_IO_REQUEST_COUNT SCI_MIN_IO_REQUESTS
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#define SCU_IO_REQUEST_SGE_COUNT SCI_MIN_SCATTER_GATHER_ELEMENTS
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#define SCU_COMPLETION_QUEUE_COUNT SCU_MIN_COMPLETION_QUEUE_ENTRIES
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#endif /* !defined(ENABLE_MINIMUM_MEMORY_OPERATION) */
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/**
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*
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*
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* The SCU_COMPLETION_QUEUE_COUNT constant indicates the size of the completion
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* queue into which the hardware DMAs 32-bit quantas (completion entries).
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*/
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/**
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*
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*
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* This queue must be programmed to a power of 2 size (e.g. 32, 64, 1024, etc.).
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*/
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#if (SCU_COMPLETION_QUEUE_COUNT != 16) && \
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(SCU_COMPLETION_QUEUE_COUNT != 32) && \
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(SCU_COMPLETION_QUEUE_COUNT != 64) && \
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(SCU_COMPLETION_QUEUE_COUNT != 128) && \
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(SCU_COMPLETION_QUEUE_COUNT != 256) && \
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(SCU_COMPLETION_QUEUE_COUNT != 512) && \
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(SCU_COMPLETION_QUEUE_COUNT != 1024)
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#error "SCU_COMPLETION_QUEUE_COUNT must be set to a power of 2."
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#endif
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#if SCU_MIN_UNSOLICITED_FRAMES > SCU_MAX_UNSOLICITED_FRAMES
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#error "Invalid configuration of unsolicited frame constants"
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#endif /* SCU_MIN_UNSOLICITED_FRAMES > SCU_MAX_UNSOLICITED_FRAMES */
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#define SCU_MIN_UF_TABLE_ENTRIES (8)
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#define SCU_ABSOLUTE_MAX_UNSOLICITED_FRAMES (4096)
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#define SCU_UNSOLICITED_FRAME_BUFFER_SIZE (1024)
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#define SCU_INVALID_FRAME_INDEX (0xFFFF)
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#define SCU_IO_REQUEST_MAX_SGE_SIZE (0x00FFFFFF)
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#define SCU_IO_REQUEST_MAX_TRANSFER_LENGTH (0x00FFFFFF)
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#endif /* _SCU_CONSTANTS_H_ */
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