From 5474405fd68ba1b7516d1cdaa68369e5e2883d6e Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Sun, 28 Jun 2009 16:19:03 +0200 Subject: Staging: rtl8187se: remove CONFIG_RTL818x_S ifdefs CONFIG_RTL818x_S is defined in drivers/staging/rtl8187se/r8180_hw.h. Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8187se/r8185b_init.c | 192 -------------------------------- 1 file changed, 192 deletions(-) (limited to 'drivers/staging/rtl8187se/r8185b_init.c') diff --git a/drivers/staging/rtl8187se/r8185b_init.c b/drivers/staging/rtl8187se/r8185b_init.c index 9647bc358ad..de111850b45 100644 --- a/drivers/staging/rtl8187se/r8185b_init.c +++ b/drivers/staging/rtl8187se/r8185b_init.c @@ -39,7 +39,6 @@ Notes: //#define CONFIG_RTL8180_IO_MAP #define TC_3W_POLL_MAX_TRY_CNT 5 -#ifdef CONFIG_RTL818X_S static u8 MAC_REG_TABLE[][2]={ //PAGA 0: // 0x34(BRSR), 0xBE(RATE_FALLBACK_CTL), 0x1E0(ARFR) would set in HwConfigureRTL8185() @@ -120,97 +119,6 @@ static u8 OFDM_CONFIG[]={ 0xC0, 0xC1, 0x58, 0xF1, 0x00, 0xC4, 0x90, 0x3e, 0xD8, 0x3C, 0x7B, 0x10, 0x10 }; -#else - static u8 MAC_REG_TABLE[][2]={ - //PAGA 0: - {0xf0, 0x32}, {0xf1, 0x32}, {0xf2, 0x00}, {0xf3, 0x00}, {0xf4, 0x32}, - {0xf5, 0x43}, {0xf6, 0x00}, {0xf7, 0x00}, {0xf8, 0x46}, {0xf9, 0xa4}, - {0xfa, 0x00}, {0xfb, 0x00}, {0xfc, 0x96}, {0xfd, 0xa4}, {0xfe, 0x00}, - {0xff, 0x00}, - - //PAGE 1: - {0x5e, 0x01}, - {0x58, 0x4b}, {0x59, 0x00}, {0x5a, 0x4b}, {0x5b, 0x00}, {0x60, 0x4b}, - {0x61, 0x09}, {0x62, 0x4b}, {0x63, 0x09}, {0xce, 0x0f}, {0xcf, 0x00}, - {0xe0, 0xff}, {0xe1, 0x0f}, {0xe2, 0x00}, {0xf0, 0x4e}, {0xf1, 0x01}, - {0xf2, 0x02}, {0xf3, 0x03}, {0xf4, 0x04}, {0xf5, 0x05}, {0xf6, 0x06}, - {0xf7, 0x07}, {0xf8, 0x08}, - - - //PAGE 2: - {0x5e, 0x02}, - {0x0c, 0x04}, {0x21, 0x61}, {0x22, 0x68}, {0x23, 0x6f}, {0x24, 0x76}, - {0x25, 0x7d}, {0x26, 0x84}, {0x27, 0x8d}, {0x4d, 0x08}, {0x4e, 0x00}, - {0x50, 0x05}, {0x51, 0xf5}, {0x52, 0x04}, {0x53, 0xa0}, {0x54, 0x1f}, - {0x55, 0x23}, {0x56, 0x45}, {0x57, 0x67}, {0x58, 0x08}, {0x59, 0x08}, - {0x5a, 0x08}, {0x5b, 0x08}, {0x60, 0x08}, {0x61, 0x08}, {0x62, 0x08}, - {0x63, 0x08}, {0x64, 0xcf}, {0x72, 0x56}, {0x73, 0x9a}, - - //PAGA 0: - {0x5e, 0x00}, - {0x34, 0xff}, {0x35, 0x0f}, {0x5b, 0x40}, {0x84, 0x88}, {0x85, 0x24}, - {0x88, 0x54}, {0x8b, 0xb8}, {0x8c, 0x07}, {0x8d, 0x00}, {0x94, 0x1b}, - {0x95, 0x12}, {0x96, 0x00}, {0x97, 0x06}, {0x9d, 0x1a}, {0x9f, 0x10}, - {0xb4, 0x22}, {0xbe, 0x80}, {0xdb, 0x00}, {0xee, 0x00}, {0x5b, 0x42}, - {0x91, 0x03}, - - //PAGE 2: - {0x5e, 0x02}, - {0x4c, 0x03}, - - //PAGE 0: - {0x5e, 0x00}, - - //PAGE 3: - {0x5e, 0x03}, - {0x9f, 0x00}, - - //PAGE 0: - {0x5e, 0x00}, - {0x8c, 0x01}, {0x8d, 0x10},{0x8e, 0x08}, {0x8f, 0x00} - }; - - -static u8 ZEBRA_AGC[]={ - 0, - 0x5e,0x5e,0x5e,0x5e,0x5d,0x5b,0x59,0x57,0x55,0x53,0x51,0x4f,0x4d,0x4b,0x49,0x47, - 0x45,0x43,0x41,0x3f,0x3d,0x3b,0x39,0x37,0x35,0x33,0x31,0x2f,0x2d,0x2b,0x29,0x27, - 0x25,0x23,0x21,0x1f,0x1d,0x1b,0x19,0x17,0x15,0x13,0x11,0x0f,0x0d,0x0b,0x09,0x07, - 0x05,0x03,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01, - 0x19,0x19,0x19,0x019,0x19,0x19,0x19,0x19,0x19,0x19,0x1e,0x1f,0x20,0x21,0x21,0x22, - 0x23,0x24,0x24,0x25,0x25,0x26,0x26,0x27,0x27,0x28,0x28,0x28,0x29,0x2a,0x2a,0x2b, - 0x2b,0x2b,0x2c,0x2c,0x2c,0x2d,0x2d,0x2d,0x2e,0x2e,0x2f,0x30,0x31,0x31,0x31,0x31, - 0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31 - }; - -static u32 ZEBRA_RF_RX_GAIN_TABLE[]={ - 0, - 0x0400,0x0401,0x0402,0x0403,0x0404,0x0405,0x0408,0x0409, - 0x040a,0x040b,0x0502,0x0503,0x0504,0x0505,0x0540,0x0541, - 0x0542,0x0543,0x0544,0x0545,0x0580,0x0581,0x0582,0x0583, - 0x0584,0x0585,0x0588,0x0589,0x058a,0x058b,0x0643,0x0644, - 0x0645,0x0680,0x0681,0x0682,0x0683,0x0684,0x0685,0x0688, - 0x0689,0x068a,0x068b,0x068c,0x0742,0x0743,0x0744,0x0745, - 0x0780,0x0781,0x0782,0x0783,0x0784,0x0785,0x0788,0x0789, - 0x078a,0x078b,0x078c,0x078d,0x0790,0x0791,0x0792,0x0793, - 0x0794,0x0795,0x0798,0x0799,0x079a,0x079b,0x079c,0x079d, - 0x07a0,0x07a1,0x07a2,0x07a3,0x07a4,0x07a5,0x07a8,0x07a9, - 0x03aa,0x03ab,0x03ac,0x03ad,0x03b0,0x03b1,0x03b2,0x03b3, - 0x03b4,0x03b5,0x03b8,0x03b9,0x03ba,0x03bb,0x03bb -}; - -// 2006.07.13, SD3 szuyitasi: -// OFDM.0x03=0x0C (original is 0x0F) -// Use the new SD3 given param, by shien chang, 2006.07.14 -static u8 OFDM_CONFIG[]={ - 0x10, 0x0d, 0x01, 0x0C, 0x14, 0xfb, 0x0f, 0x60, 0x00, 0x60, - 0x00, 0x00, 0x00, 0x5c, 0x00, 0x00, 0x40, 0x00, 0x40, 0x00, - 0x00, 0x00, 0xa8, 0x46, 0xb2, 0x33, 0x07, 0xa5, 0x6f, 0x55, - 0xc8, 0xb3, 0x0a, 0xe1, 0x1c, 0x8a, 0xb6, 0x83, 0x34, 0x0f, - 0x4f, 0x23, 0x6f, 0xc2, 0x6b, 0x40, 0x80, 0x00, 0xc0, 0xc1, - 0x58, 0xf1, 0x00, 0xe4, 0x90, 0x3e, 0x6d, 0x3c, 0xff, 0x07 -}; -#endif /*--------------------------------------------------------------- * Hardware IO @@ -538,12 +446,10 @@ ZEBRA_RFSerialWrite( u16 UshortBuffer; u8 u1bTmp; -#ifdef CONFIG_RTL818X_S // RTL8187S HSSI Read/Write Function u1bTmp = read_nic_byte(dev, RF_SW_CONFIG); u1bTmp |= RF_SW_CFG_SI; //reg08[1]=1 Serial Interface(SI) write_nic_byte(dev, RF_SW_CONFIG, u1bTmp); -#endif UshortBuffer = read_nic_word(dev, RFPinsOutput); oval = UshortBuffer & 0xfff8; // We shall clear bit0, 1, 2 first, 2005.10.28, by rcnjko. @@ -914,7 +820,6 @@ RF_WriteReg( 1); // bWrite } break; - #ifdef CONFIG_RTL818X_S case HW_THREE_WIRE_PI: //Parallel Interface { // Pure HW 3-wire. data2Write = (data << 4) | (u32)(offset & 0x0f); @@ -948,7 +853,6 @@ RF_WriteReg( // printk(" exit ZEBRA_RFSerialWrite\n "); } break; - #endif default: @@ -981,13 +885,11 @@ ZEBRA_RFSerialRead( u8 u1bTmp; ThreeWireReg tdata; //PHAL_DATA_8187 pHalData = GetHalData8187(pAdapter); -#ifdef CONFIG_RTL818X_S { // RTL8187S HSSI Read/Write Function u1bTmp = read_nic_byte(dev, RF_SW_CONFIG); u1bTmp |= RF_SW_CFG_SI; //reg08[1]=1 Serial Interface(SI) write_nic_byte(dev, RF_SW_CONFIG, u1bTmp); } -#endif wReg80 = oval = read_nic_word(dev, RFPinsOutput); oval2 = read_nic_word(dev, RFPinsEnable); @@ -1111,7 +1013,6 @@ RF_ReadReg( case RF_ZEBRA4: switch(priv->RegThreeWireMode) { -#ifdef CONFIG_RTL818X_S case HW_THREE_WIRE_PI: // For 87S Parallel Interface. { data2Write = ((u32)(offset&0x0f)); @@ -1141,7 +1042,6 @@ RF_ReadReg( } break; -#endif // Perform SW 3-wire programming by driver. default: { @@ -1200,7 +1100,6 @@ ReadBBPortUchar( return RegisterContent; } //{by amy 080312 -#ifdef CONFIG_RTL818X_S // // Description: // Perform Antenna settings with antenna diversity on 87SE. @@ -1282,7 +1181,6 @@ SetAntennaConfig87SE( priv->CurrAntennaIndex = DefaultAnt; // Update default settings. return bAntennaSwitched; } -#endif //by amy 080312 /*--------------------------------------------------------------- * Hardware Initialization. @@ -1301,7 +1199,6 @@ ZEBRA_Config_85BASIC_HardCode( u32 u4bRegOffset, u4bRegValue, u4bRF23, u4bRF24; u8 u1b24E; -#ifdef CONFIG_RTL818X_S //============================================================================= // 87S_PCIE :: RADIOCFG.TXT @@ -1509,72 +1406,6 @@ ZEBRA_Config_85BASIC_HardCode( write_nic_byte(dev, CCK_TXAGC, 0x10); write_nic_byte(dev, OFDM_TXAGC, 0x1B); write_nic_byte(dev, ANTSEL, 0x03); -#else - //============================================================================= - // RADIOCFG.TXT - //============================================================================= - - RF_WriteReg(dev, 0x00, 0x00b7); mdelay(1); - RF_WriteReg(dev, 0x01, 0x0ee0); mdelay(1); - RF_WriteReg(dev, 0x02, 0x044d); mdelay(1); - RF_WriteReg(dev, 0x03, 0x0441); mdelay(1); - RF_WriteReg(dev, 0x04, 0x08c3); mdelay(1); - RF_WriteReg(dev, 0x05, 0x0c72); mdelay(1); - RF_WriteReg(dev, 0x06, 0x00e6); mdelay(1); - RF_WriteReg(dev, 0x07, 0x082a); mdelay(1); - RF_WriteReg(dev, 0x08, 0x003f); mdelay(1); - RF_WriteReg(dev, 0x09, 0x0335); mdelay(1); - RF_WriteReg(dev, 0x0a, 0x09d4); mdelay(1); - RF_WriteReg(dev, 0x0b, 0x07bb); mdelay(1); - RF_WriteReg(dev, 0x0c, 0x0850); mdelay(1); - RF_WriteReg(dev, 0x0d, 0x0cdf); mdelay(1); - RF_WriteReg(dev, 0x0e, 0x002b); mdelay(1); - RF_WriteReg(dev, 0x0f, 0x0114); mdelay(1); - - RF_WriteReg(dev, 0x00, 0x01b7); mdelay(1); - - - for(i=1;i<=95;i++) - { - RF_WriteReg(dev, 0x01, i); mdelay(1); - RF_WriteReg(dev, 0x02, ZEBRA_RF_RX_GAIN_TABLE[i]); mdelay(1); - //DbgPrint("RF - 0x%x = 0x%x", i, ZEBRA_RF_RX_GAIN_TABLE[i]); - } - - RF_WriteReg(dev, 0x03, 0x0080); mdelay(1); // write reg 18 - RF_WriteReg(dev, 0x05, 0x0004); mdelay(1); // write reg 20 - RF_WriteReg(dev, 0x00, 0x00b7); mdelay(1); // switch to reg0-reg15 - //0xfd - //0xfd - //0xfd - RF_WriteReg(dev, 0x02, 0x0c4d); mdelay(1); - mdelay(100); // Deay 100 ms. //0xfe - mdelay(100); // Deay 100 ms. //0xfe - RF_WriteReg(dev, 0x02, 0x044d); mdelay(1); - RF_WriteReg(dev, 0x00, 0x02bf); mdelay(1); //0x002f disable 6us corner change, 06f--> enable - - //============================================================================= - - //============================================================================= - // CCKCONF.TXT - //============================================================================= - - //============================================================================= - - //============================================================================= - // Follow WMAC RTL8225_Config() - //============================================================================= - - // power control - write_nic_byte(dev, CCK_TXAGC, 0x03); - write_nic_byte(dev, OFDM_TXAGC, 0x07); - write_nic_byte(dev, ANTSEL, 0x03); - - //============================================================================= - - // OFDM BBP setup -// SetOutputEnableOfRfPins(dev);//by amy -#endif @@ -1629,10 +1460,8 @@ ZEBRA_Config_85BASIC_HardCode( //by amy for antenna //============================================================================= //{by amy 080312 -#ifdef CONFIG_RTL818X_S // Config Sw/Hw Combinational Antenna Diversity. Added by Roger, 2008.02.26. SetAntennaConfig87SE(dev, priv->bDefaultAntenna1, priv->bSwAntennaDiverity); -#endif //by amy 080312} #if 0 // Config Sw/Hw Antenna Diversity @@ -1857,7 +1686,6 @@ UpdateInitialGain( break; } } -#ifdef CONFIG_RTL818X_S // // Description: // Tx Power tracking mechanism routine on 87SE. @@ -1878,7 +1706,6 @@ InitTxPwrTracking87SE( RF_WriteReg(dev, 0x02, u4bRfReg|PWR_METER_EN); mdelay(1); } -#endif void PhyConfig8185( struct net_device *dev @@ -1896,7 +1723,6 @@ PhyConfig8185( break; } //{by amy 080312 -#ifdef CONFIG_RTL818X_S // Set default initial gain state to 4, approved by SD3 DZ, by Bruce, 2007-06-06. if(priv->bDigMechanism) { @@ -1913,7 +1739,6 @@ PhyConfig8185( if(priv->bTxPowerTrack) InitTxPwrTracking87SE(dev); -#endif //by amy 080312} priv->InitialGainBackUp= priv->InitialGain; UpdateInitialGain(dev); @@ -2004,13 +1829,8 @@ HwConfigureRTL8185( #if 0 PlatformIOWrite2Byte(dev, ARFR, 0x0fff); // set 1M ~ 54M #endif -#ifdef CONFIG_RTL818X_S // Aadded by Roger, 2007.11.15. PlatformIOWrite2Byte(dev, ARFR, 0x0fff); //set 1M ~ 54Mbps. -#else - PlatformIOWrite2Byte(dev, ARFR, 0x0c00); //set 48Mbps, 54Mbps. - // By SD3 szuyi's request. by Roger, 2007.03.26. -#endif //by amy } else @@ -2083,7 +1903,6 @@ MacConfig_85BASIC( #if 0 write_nic_dword(dev, RFTiming, 0x00004001); #endif -#ifdef CONFIG_RTL818X_S // power save parameter based on "87SE power save parameters 20071127.doc", as follow. //Enable DA10 TX power saving @@ -2104,9 +1923,6 @@ MacConfig_85BASIC( write_nic_word(dev, 0x37C, 0x00EC); // write_nic_word(dev, 0x37E, 0x00FE);//-edward write_nic_word(dev, 0x37E, 0x00EC);//+edward -#else - write_nic_dword(dev, RFTiming, 0x00004003); -#endif write_nic_byte(dev, 0x24E,0x01); //by amy @@ -2973,22 +2789,14 @@ void rtl8185b_adapter_start(struct net_device *dev) write_nic_byte(dev, CR9346, 0xc0); // enable config register write //by amy tmpu8 = read_nic_byte(dev, CONFIG3); -#ifdef CONFIG_RTL818X_S write_nic_byte(dev, CONFIG3, (tmpu8 |CONFIG3_PARM_En) ); -#else - write_nic_byte(dev, CONFIG3, (tmpu8 |CONFIG3_PARM_En | CONFIG3_CLKRUN_En) ); -#endif //by amy // Turn on Analog power. // Asked for by William, otherwise, MAC 3-wire can't work, 2006.06.27, by rcnjko. write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON); write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON); //by amy -#ifdef CONFIG_RTL818X_S write_nic_word(dev, ANAPARAM3, 0x0010); -#else - write_nic_byte(dev, ANAPARAM3, 0x00); -#endif //by amy write_nic_byte(dev, CONFIG3, tmpu8); -- cgit v1.2.3