From 0b9b18e0166d8925ed222335efbc3cfd66aa882f Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 9 Jul 2012 23:26:58 -0500 Subject: ARM: mv78xx0: use fixed pci i/o mapping Move mv78xx0 PCI to fixed i/o mapping and remove io.h. This changes the PCI bus addresses from the cpu address to 0 based. It appears that there is translation h/w for this, but its untested. Signed-off-by: Rob Herring Cc: Jason Cooper Cc: Andrew Lunn Reviewed-by: Arnd Bergmann --- arch/arm/mach-mv78xx0/include/mach/io.h | 24 ------------------------ arch/arm/mach-mv78xx0/include/mach/mv78xx0.h | 21 ++++++++++----------- 2 files changed, 10 insertions(+), 35 deletions(-) delete mode 100644 arch/arm/mach-mv78xx0/include/mach/io.h (limited to 'arch/arm/mach-mv78xx0/include') diff --git a/arch/arm/mach-mv78xx0/include/mach/io.h b/arch/arm/mach-mv78xx0/include/mach/io.h deleted file mode 100644 index c7d9d00d8fc..00000000000 --- a/arch/arm/mach-mv78xx0/include/mach/io.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/io.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_IO_H -#define __ASM_ARCH_IO_H - -#include "mv78xx0.h" - -#define IO_SPACE_LIMIT 0xffffffff - -static inline void __iomem *__io(unsigned long addr) -{ - return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0)) - + MV78XX0_PCIE_IO_VIRT_BASE(0)); -} - -#define __io(a) __io(a) - -#endif diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index e807c4c52a0..bd03fed1128 100644 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h @@ -29,15 +29,15 @@ * * virt phys size * fe400000 f102x000 16K core-specific peripheral registers - * fe700000 f0800000 1M PCIe #0 I/O space - * fe800000 f0900000 1M PCIe #1 I/O space - * fe900000 f0a00000 1M PCIe #2 I/O space - * fea00000 f0b00000 1M PCIe #3 I/O space - * feb00000 f0c00000 1M PCIe #4 I/O space - * fec00000 f0d00000 1M PCIe #5 I/O space - * fed00000 f0e00000 1M PCIe #6 I/O space - * fee00000 f0f00000 1M PCIe #7 I/O space - * fef00000 f1000000 1M on-chip peripheral registers + * fee00000 f0800000 64K PCIe #0 I/O space + * fee10000 f0900000 64K PCIe #1 I/O space + * fee20000 f0a00000 64K PCIe #2 I/O space + * fee30000 f0b00000 64K PCIe #3 I/O space + * fee40000 f0c00000 64K PCIe #4 I/O space + * fee50000 f0d00000 64K PCIe #5 I/O space + * fee60000 f0e00000 64K PCIe #6 I/O space + * fee70000 f0f00000 64K PCIe #7 I/O space + * fd000000 f1000000 1M on-chip peripheral registers */ #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 @@ -46,11 +46,10 @@ #define MV78XX0_CORE_REGS_SIZE SZ_16K #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) -#define MV78XX0_PCIE_IO_VIRT_BASE(i) (0xfe700000 + ((i) << 20)) #define MV78XX0_PCIE_IO_SIZE SZ_1M #define MV78XX0_REGS_PHYS_BASE 0xf1000000 -#define MV78XX0_REGS_VIRT_BASE 0xfef00000 +#define MV78XX0_REGS_VIRT_BASE 0xfd000000 #define MV78XX0_REGS_SIZE SZ_1M #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 -- cgit v1.2.3 From 5ae9f5dbb3376c14201f8354d857485ff3ea14af Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:16 +0200 Subject: arm: mach-mv78xx0: use plus instead of or for address definitions Since we are going to use IOMEM() to define many base virtual addresses, we can no longer use binary or to define the individual register addresses ("binary or" arithmetic on pointers is not allowed). Instead, use the more conventional plus operator to do so. The binary or operators were actually not useful because the low-order bits of the base address were always zero, so the usage of the binary or operators was effectively identical to a plus operator. Signed-off-by: Thomas Petazzoni Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-mv78xx0/include/mach/bridge-regs.h | 12 ++-- arch/arm/mach-mv78xx0/include/mach/mv78xx0.h | 82 ++++++++++++------------ 2 files changed, 47 insertions(+), 47 deletions(-) (limited to 'arch/arm/mach-mv78xx0/include') diff --git a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h index eb187e0e059..5f03484584d 100644 --- a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h +++ b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h @@ -11,18 +11,18 @@ #include -#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) +#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) #define L2_WRITETHROUGH 0x00020000 -#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) +#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) #define SOFT_RESET_OUT_EN 0x00000004 -#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) +#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) #define SOFT_RESET 0x00000001 #define BRIDGE_INT_TIMER1_CLR (~0x0004) -#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) +#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) #define IRQ_CAUSE_ERR_OFF 0x0000 #define IRQ_CAUSE_LOW_OFF 0x0004 #define IRQ_CAUSE_HIGH_OFF 0x0008 @@ -30,7 +30,7 @@ #define IRQ_MASK_LOW_OFF 0x0010 #define IRQ_MASK_HIGH_OFF 0x0014 -#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) -#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300) +#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) +#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) #endif diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index e807c4c52a0..a86e79ecfea 100644 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h @@ -65,47 +65,47 @@ /* * Register Map */ -#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000) -#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE | 0x1500) -#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1570) - -#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x10000) -#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000) -#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030) -#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034) -#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0100) -#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000) -#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1100) -#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) -#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) -#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) -#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) -#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2200) -#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2200) -#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2300) -#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2300) - -#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x30000) -#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x34000) - -#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x40000) -#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x44000) -#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x48000) -#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x4c000) - -#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x50000) -#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x51000) -#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x52000) - -#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x70000) -#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x74000) - -#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x80000) -#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x84000) -#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x88000) -#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x8c000) - -#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000) +#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000) +#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE + 0x1500) +#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE + 0x1570) + +#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000) +#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000) +#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE + 0x0030) +#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE + 0x0034) +#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100) +#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000) +#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1100) +#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000) +#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000) +#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100) +#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100) +#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2200) +#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2200) +#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2300) +#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2300) + +#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x30000) +#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x34000) + +#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x40000) +#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x44000) +#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x48000) +#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x4c000) + +#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x50000) +#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x51000) +#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x52000) + +#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x70000) +#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x74000) + +#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x80000) +#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x84000) +#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000) +#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000) + +#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0xa0000) /* * Supported devices and revisions. -- cgit v1.2.3 From 383b99610e6084878930d4e4682dfc5e9141b038 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:20 +0200 Subject: arm: mach-mv78xx0: use IOMEM() for base address definitions We now define all virtual base address constants using IOMEM() so that those are naturally typed as void __iomem pointers, and we do the necessary adjustements in the mach-mv78xx0 code. Note that we introduce a few temporary additional "unsigned long" casts when calling into plat-orion functions. Those are removed by followup patches converting plat-orion functions to void __iomem pointers as well. Signed-off-by: Thomas Petazzoni Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-mv78xx0/include/mach/mv78xx0.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm/mach-mv78xx0/include') diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index a86e79ecfea..62405e8dda0 100644 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h @@ -41,16 +41,16 @@ */ #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 -#define MV78XX0_CORE_REGS_VIRT_BASE 0xfe400000 +#define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000) #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000 #define MV78XX0_CORE_REGS_SIZE SZ_16K #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) -#define MV78XX0_PCIE_IO_VIRT_BASE(i) (0xfe700000 + ((i) << 20)) +#define MV78XX0_PCIE_IO_VIRT_BASE(i) IOMEM(0xfe700000 + ((i) << 20)) #define MV78XX0_PCIE_IO_SIZE SZ_1M #define MV78XX0_REGS_PHYS_BASE 0xf1000000 -#define MV78XX0_REGS_VIRT_BASE 0xfef00000 +#define MV78XX0_REGS_VIRT_BASE IOMEM(0xfef00000) #define MV78XX0_REGS_SIZE SZ_1M #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 -- cgit v1.2.3