From 639da5ee374ba8f070690bbd355ca30139ce145a Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Wed, 31 Aug 2011 22:55:46 -0400 Subject: ARM: add an extra temp register to the low level debugging addruart macro Some platforms (like OMAP not to name it) are doing rather complicated hacks just to determine the base UART address to use. Let's give their addruart macro some slack by providing an extra work register which will allow for much needed cleanups. This is basically a no-op as this commit is only adding the extra argument to the macro but no one is using it yet. Signed-off-by: nicolas Pitre Reviewed-by: Kevin Hilman --- arch/arm/mach-msm/include/mach/debug-macro.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-msm/include') diff --git a/arch/arm/mach-msm/include/mach/debug-macro.S b/arch/arm/mach-msm/include/mach/debug-macro.S index 646b99ebc77..2dc73ccddb1 100644 --- a/arch/arm/mach-msm/include/mach/debug-macro.S +++ b/arch/arm/mach-msm/include/mach/debug-macro.S @@ -20,7 +20,7 @@ #include #if defined(CONFIG_HAS_MSM_DEBUG_UART_PHYS) && !defined(CONFIG_MSM_DEBUG_UART_NONE) - .macro addruart, rp, rv + .macro addruart, rp, rv, tmp ldr \rp, =MSM_DEBUG_UART_PHYS ldr \rv, =MSM_DEBUG_UART_BASE .endm @@ -37,7 +37,7 @@ beq 1001b .endm #else - .macro addruart, rp, rv + .macro addruart, rp, rv, tmp mov \rv, #0xff000000 orr \rv, \rv, #0x00f00000 .endm -- cgit v1.2.3 From 9d25544968f831e97e858bd8ec2933f225126ca8 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Tue, 5 Jul 2011 22:52:54 -0400 Subject: ARM: mach-msm: remove mach/memory.h Signed-off-by: Nicolas Pitre --- arch/arm/mach-msm/include/mach/memory.h | 35 --------------------------------- 1 file changed, 35 deletions(-) delete mode 100644 arch/arm/mach-msm/include/mach/memory.h (limited to 'arch/arm/mach-msm/include') diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h deleted file mode 100644 index 58d5e7eec43..00000000000 --- a/arch/arm/mach-msm/include/mach/memory.h +++ /dev/null @@ -1,35 +0,0 @@ -/* arch/arm/mach-msm/include/mach/memory.h - * - * Copyright (C) 2007 Google, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -/* physical offset of RAM */ -#if defined(CONFIG_ARCH_QSD8X50) && defined(CONFIG_MSM_SOC_REV_A) -#define PLAT_PHYS_OFFSET UL(0x00000000) -#elif defined(CONFIG_ARCH_QSD8X50) -#define PLAT_PHYS_OFFSET UL(0x20000000) -#elif defined(CONFIG_ARCH_MSM7X30) -#define PLAT_PHYS_OFFSET UL(0x00000000) -#elif defined(CONFIG_ARCH_MSM8X60) -#define PLAT_PHYS_OFFSET UL(0x40000000) -#elif defined(CONFIG_ARCH_MSM8960) -#define PLAT_PHYS_OFFSET UL(0x40000000) -#else -#define PLAT_PHYS_OFFSET UL(0x10000000) -#endif - -#endif - -- cgit v1.2.3 From 292b293ceef2eda1f96f0c90b96e954d7bdabd1c Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Wed, 20 Jul 2011 16:24:14 +0100 Subject: ARM: gic: consolidate PPI handling PPI handling is a bit of an odd beast. It uses its own low level handling code and is hardwired to the local timers (hence lacking a registration interface). Instead, switch the low handling to the normal SPI handling code. PPIs are handled by the handle_percpu_devid_irq flow. This also allows the removal of some duplicated code. Cc: Kukjin Kim Cc: David Brown Cc: Bryan Huntsman Cc: Tony Lindgren Cc: Paul Mundt Cc: Magnus Damm Cc: Thomas Gleixner Acked-by: David Brown Tested-by: David Brown Tested-by: Shawn Guo Signed-off-by: Marc Zyngier --- arch/arm/mach-msm/include/mach/entry-macro-qgic.S | 73 +---------------------- 1 file changed, 1 insertion(+), 72 deletions(-) (limited to 'arch/arm/mach-msm/include') diff --git a/arch/arm/mach-msm/include/mach/entry-macro-qgic.S b/arch/arm/mach-msm/include/mach/entry-macro-qgic.S index 12467157afb..717076f3ca7 100644 --- a/arch/arm/mach-msm/include/mach/entry-macro-qgic.S +++ b/arch/arm/mach-msm/include/mach/entry-macro-qgic.S @@ -8,81 +8,10 @@ * warranty of any kind, whether express or implied. */ -#include -#include +#include .macro disable_fiq .endm - .macro get_irqnr_preamble, base, tmp - ldr \base, =gic_cpu_base_addr - ldr \base, [\base] - .endm - .macro arch_ret_to_user, tmp1, tmp2 .endm - - /* - * The interrupt numbering scheme is defined in the - * interrupt controller spec. To wit: - * - * Migrated the code from ARM MP port to be more consistent - * with interrupt processing , the following still holds true - * however, all interrupts are treated the same regardless of - * if they are local IPI or PPI - * - * Interrupts 0-15 are IPI - * 16-31 are PPI - * (16-18 are the timers) - * 32-1020 are global - * 1021-1022 are reserved - * 1023 is "spurious" (no interrupt) - * - * A simple read from the controller will tell us the number of the - * highest priority enabled interrupt. We then just need to check - * whether it is in the valid range for an IRQ (0-1020 inclusive). - * - * Base ARM code assumes that the local (private) peripheral interrupts - * are not valid, we treat them differently, in that the privates are - * handled like normal shared interrupts with the exception that only - * one processor can register the interrupt and the handler must be - * the same for all processors. - */ - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - - ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 =srcCPU, - 9-0 =int # */ - - bic \irqnr, \irqstat, #0x1c00 @mask src - cmp \irqnr, #15 - ldr \tmp, =1021 - cmpcc \irqnr, \irqnr - cmpne \irqnr, \tmp - cmpcs \irqnr, \irqnr - - .endm - - /* We assume that irqstat (the raw value of the IRQ acknowledge - * register) is preserved from the macro above. - * If there is an IPI, we immediately signal end of interrupt on the - * controller, since this requires the original irqstat value which - * we won't easily be able to recreate later. - */ - .macro test_for_ipi, irqnr, irqstat, base, tmp - bic \irqnr, \irqstat, #0x1c00 - cmp \irqnr, #16 - strcc \irqstat, [\base, #GIC_CPU_EOI] - cmpcs \irqnr, \irqnr - .endm - - /* As above, this assumes that irqstat and base are preserved.. */ - - .macro test_for_ltirq, irqnr, irqstat, base, tmp - bic \irqnr, \irqstat, #0x1c00 - mov \tmp, #0 - cmp \irqnr, #16 - moveq \tmp, #1 - streq \irqstat, [\base, #GIC_CPU_EOI] - cmp \tmp, #0 - .endm -- cgit v1.2.3