From afc49177b412dfe547c60740ac1f1db7f805da43 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Tue, 21 Aug 2012 20:59:33 +0400 Subject: ARM: clps711x: Fix register definitions This patch contain some fixes: - Fixes the address of register PORTE. - Corrects name for DAIDR0 register. - Removes unused definition for SYNCIO_CFGLEN. - Fixes definition SYNCIO_FRMLEN. Signed-off-by: Alexander Shiyan --- arch/arm/mach-clps711x/include/mach/clps711x.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'arch/arm/mach-clps711x/include/mach/clps711x.h') diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h index 1dd806f2847..c82e21ca49c 100644 --- a/arch/arm/mach-clps711x/include/mach/clps711x.h +++ b/arch/arm/mach-clps711x/include/mach/clps711x.h @@ -31,8 +31,8 @@ #define PBDDR (0x0041) #define PCDDR (0x0042) #define PDDDR (0x0043) -#define PEDR (0x0080) -#define PEDDR (0x00c0) +#define PEDR (0x0083) +#define PEDDR (0x00c3) #define SYSCON1 (0x0100) #define SYSFLG1 (0x0140) #define MEMCFG1 (0x0180) @@ -77,7 +77,7 @@ #define KBDEOI (0x1700) #define DAIR (0x2000) -#define DAIR0 (0x2040) +#define DAIDR0 (0x2040) #define DAIDR1 (0x2080) #define DAIDR2 (0x20c0) #define DAISR (0x2100) @@ -191,8 +191,7 @@ #define UBRLCR_WRDLEN8 (3 << 17) #define UBRLCR_WRDLEN_MASK (3 << 17) -#define SYNCIO_FRMLEN(x) (((x) & 0x3f) << 7) -#define SYNCIO_CFGLEN(x) ((x) & 0x7f) +#define SYNCIO_FRMLEN(x) (((x) & 0x1f) << 8) #define SYNCIO_SMCKEN (1 << 13) #define SYNCIO_TXFRMEN (1 << 14) -- cgit v1.2.3 From 36504ac131d14611dded451dd8b9f8426d084111 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 10 Oct 2012 19:45:30 +0400 Subject: ARM: clps711x: added missing definitions Signed-off-by: Alexander Shiyan Signed-off-by: Arnd Bergmann --- arch/arm/mach-clps711x/include/mach/clps711x.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/mach-clps711x/include/mach/clps711x.h') diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h index c82e21ca49c..aee352c00a1 100644 --- a/arch/arm/mach-clps711x/include/mach/clps711x.h +++ b/arch/arm/mach-clps711x/include/mach/clps711x.h @@ -257,6 +257,9 @@ #define MEMCFG_BUS_WIDTH_16 (0) #define MEMCFG_BUS_WIDTH_8 (3) +#define MEMCFG_SQAEN (1 << 6) +#define MEMCFG_CLKENB (1 << 7) + #define MEMCFG_WAITSTATE_8_3 (0 << 2) #define MEMCFG_WAITSTATE_7_3 (1 << 2) #define MEMCFG_WAITSTATE_6_3 (2 << 2) -- cgit v1.2.3 From 0d8be81c0e15ad8ebdd35bbbeb35b03f85a4b558 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sat, 17 Nov 2012 17:57:13 +0400 Subject: ARM: clps711x: Implement usage "SPARSE_IRQ" kernel option for a platform Signed-off-by: Alexander Shiyan Signed-off-by: Olof Johansson --- arch/arm/mach-clps711x/include/mach/clps711x.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm/mach-clps711x/include/mach/clps711x.h') diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h index aee352c00a1..1f4728d414d 100644 --- a/arch/arm/mach-clps711x/include/mach/clps711x.h +++ b/arch/arm/mach-clps711x/include/mach/clps711x.h @@ -277,4 +277,25 @@ #define MEMCFG_WAITSTATE_2_0 (14 << 2) #define MEMCFG_WAITSTATE_1_0 (15 << 2) +/* INTSR1 Interrupts */ +#define IRQ_CSINT (4) +#define IRQ_EINT1 (5) +#define IRQ_EINT2 (6) +#define IRQ_EINT3 (7) +#define IRQ_TC1OI (8) +#define IRQ_TC2OI (9) +#define IRQ_RTCMI (10) +#define IRQ_TINT (11) +#define IRQ_UTXINT1 (12) +#define IRQ_URXINT1 (13) +#define IRQ_UMSINT (14) +#define IRQ_SSEOTI (15) + +/* INTSR2 Interrupts */ +#define IRQ_KBDINT (16 + 0) +#define IRQ_SS2RX (16 + 1) +#define IRQ_SS2TX (16 + 2) +#define IRQ_UTXINT2 (16 + 12) +#define IRQ_URXINT2 (16 + 13) + #endif /* __MACH_CLPS711X_H */ -- cgit v1.2.3 From 197926108cc837474f8807678d6220bdce281620 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sat, 17 Nov 2012 17:57:15 +0400 Subject: ARM: clps711x: Add FIQ interrupt handling CLPS711X-target CPU can have a several FIQ interrupts. With this patch we adds handling for a one which will be used for ALSA PCM later. Since FIQ have a separate handler we only add "mask" and "unmask" calls which will used for enable/disable_irq functions. Signed-off-by: Alexander Shiyan Signed-off-by: Olof Johansson --- arch/arm/mach-clps711x/include/mach/clps711x.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/mach-clps711x/include/mach/clps711x.h') diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h index 1f4728d414d..01d1b955971 100644 --- a/arch/arm/mach-clps711x/include/mach/clps711x.h +++ b/arch/arm/mach-clps711x/include/mach/clps711x.h @@ -298,4 +298,7 @@ #define IRQ_UTXINT2 (16 + 12) #define IRQ_URXINT2 (16 + 13) +/* INTSR3 Interrupts */ +#define IRQ_DAIINT (32 + 0) + #endif /* __MACH_CLPS711X_H */ -- cgit v1.2.3