From c3545236e8740ab556022f87685d18503c86e187 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Mon, 1 Oct 2012 10:59:29 +0100 Subject: ARM: 7546/1: cache-l2x0: add an optional register to save/restore Tested-and-Reviewed-by: Yehuda Yitschak Tested-and-Reviewed-by: Lior Amsalem Signed-off-by: Gregory CLEMENT Signed-off-by: Russell King --- arch/arm/include/asm/hardware/cache-l2x0.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include/asm/hardware/cache-l2x0.h') diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index c4c87bc1223..5f2c7b44fda 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -126,6 +126,7 @@ struct l2x0_regs { unsigned long filter_end; unsigned long prefetch_ctrl; unsigned long pwr_ctrl; + unsigned long ctrl; }; extern struct l2x0_regs l2x0_saved_regs; -- cgit v1.2.3 From b8db6b886a1fecd6a5b1d13b190f3149247305ef Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Tue, 6 Nov 2012 01:58:07 +0100 Subject: ARM: 7547/4: cache-l2x0: add support for Aurora L2 cache ctrl Aurora Cache Controller was designed to be compatible with the ARM L2 Cache Controller. It comes with some difference or improvement such as: - no cache id part number available through hardware (need to get it by the DT). - always write through mode available. - two flavors of the controller outer cache and system cache (meaning maintenance operations on L1 are broadcasted to the L2 and L2 performs the same operation). - in outer cache mode, the cache maintenance operations are improved and can be done on a range inside a page and are not limited to a cache line. Tested-and-Reviewed-by: Lior Amsalem Signed-off-by: Gregory CLEMENT Signed-off-by: Yehuda Yitschak Reviewed-by: Will Deacon Signed-off-by: Russell King --- arch/arm/include/asm/hardware/cache-l2x0.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/include/asm/hardware/cache-l2x0.h') diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index 5f2c7b44fda..3b2c40b5bfa 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -102,6 +102,10 @@ #define L2X0_ADDR_FILTER_EN 1 +#define L2X0_CTRL_EN 1 + +#define L2X0_WAY_SIZE_SHIFT 3 + #ifndef __ASSEMBLY__ extern void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask); #if defined(CONFIG_CACHE_L2X0) && defined(CONFIG_OF) -- cgit v1.2.3