From 96433f6ee49032d7a8bda76de2b05cfde2914354 Mon Sep 17 00:00:00 2001 From: David Howells Date: Mon, 17 Dec 2012 13:47:09 +0000 Subject: UAPI: (Scripted) Disintegrate arch/alpha/include/asm Signed-off-by: David Howells Acked-by: Arnd Bergmann Acked-by: Thomas Gleixner Acked-by: Michael Kerrisk Acked-by: Paul E. McKenney Acked-by: Dave Jones Acked-by: Michael Cree Acked-by: Matt Turner --- arch/alpha/include/uapi/asm/auxvec.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 arch/alpha/include/uapi/asm/auxvec.h (limited to 'arch/alpha/include/uapi/asm/auxvec.h') diff --git a/arch/alpha/include/uapi/asm/auxvec.h b/arch/alpha/include/uapi/asm/auxvec.h new file mode 100644 index 00000000000..a3a579dfdb4 --- /dev/null +++ b/arch/alpha/include/uapi/asm/auxvec.h @@ -0,0 +1,26 @@ +#ifndef __ASM_ALPHA_AUXVEC_H +#define __ASM_ALPHA_AUXVEC_H + +/* Reserve these numbers for any future use of a VDSO. */ +#if 0 +#define AT_SYSINFO 32 +#define AT_SYSINFO_EHDR 33 +#endif + +/* More complete cache descriptions than AT_[DIU]CACHEBSIZE. If the + value is -1, then the cache doesn't exist. Otherwise: + + bit 0-3: Cache set-associativity; 0 means fully associative. + bit 4-7: Log2 of cacheline size. + bit 8-31: Size of the entire cache >> 8. + bit 32-63: Reserved. +*/ + +#define AT_L1I_CACHESHAPE 34 +#define AT_L1D_CACHESHAPE 35 +#define AT_L2_CACHESHAPE 36 +#define AT_L3_CACHESHAPE 37 + +#define AT_VECTOR_SIZE_ARCH 4 /* entries in ARCH_DLINFO */ + +#endif /* __ASM_ALPHA_AUXVEC_H */ -- cgit v1.2.3