From 0be421862b857e61964435ffcaa7499cf77a5e5a Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Sun, 19 Aug 2012 14:41:02 +1200 Subject: alpha: fix fpu.h usage in userspace After commit ec2212088c42 ("Disintegrate asm/system.h for Alpha"), the fpu.h header which we install for userland started depending on special_insns.h which is not installed. However, fpu.h only uses that for __KERNEL__ code, so protect the inclusion the same way to avoid build breakage in glibc: /usr/include/asm/fpu.h:4:31: fatal error: asm/special_insns.h: No such file or directory Cc: stable@vger.kernel.org Reported-by: Matt Turner Signed-off-by: Mike Frysinger Signed-off-by: Michael Cree Acked-by: Matt Turner Signed-off-by: Linus Torvalds --- arch/alpha/include/asm/fpu.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/alpha/include/asm/fpu.h') diff --git a/arch/alpha/include/asm/fpu.h b/arch/alpha/include/asm/fpu.h index db00f7885fa..e477bcd5b94 100644 --- a/arch/alpha/include/asm/fpu.h +++ b/arch/alpha/include/asm/fpu.h @@ -1,7 +1,9 @@ #ifndef __ASM_ALPHA_FPU_H #define __ASM_ALPHA_FPU_H +#ifdef __KERNEL__ #include +#endif /* * Alpha floating-point control register defines: -- cgit v1.2.3 From 96433f6ee49032d7a8bda76de2b05cfde2914354 Mon Sep 17 00:00:00 2001 From: David Howells Date: Mon, 17 Dec 2012 13:47:09 +0000 Subject: UAPI: (Scripted) Disintegrate arch/alpha/include/asm Signed-off-by: David Howells Acked-by: Arnd Bergmann Acked-by: Thomas Gleixner Acked-by: Michael Kerrisk Acked-by: Paul E. McKenney Acked-by: Dave Jones Acked-by: Michael Cree Acked-by: Matt Turner --- arch/alpha/include/asm/fpu.h | 124 +------------------------------------------ 1 file changed, 1 insertion(+), 123 deletions(-) (limited to 'arch/alpha/include/asm/fpu.h') diff --git a/arch/alpha/include/asm/fpu.h b/arch/alpha/include/asm/fpu.h index e477bcd5b94..71c20956b90 100644 --- a/arch/alpha/include/asm/fpu.h +++ b/arch/alpha/include/asm/fpu.h @@ -1,128 +1,8 @@ #ifndef __ASM_ALPHA_FPU_H #define __ASM_ALPHA_FPU_H -#ifdef __KERNEL__ #include -#endif - -/* - * Alpha floating-point control register defines: - */ -#define FPCR_DNOD (1UL<<47) /* denorm INV trap disable */ -#define FPCR_DNZ (1UL<<48) /* denorms to zero */ -#define FPCR_INVD (1UL<<49) /* invalid op disable (opt.) */ -#define FPCR_DZED (1UL<<50) /* division by zero disable (opt.) */ -#define FPCR_OVFD (1UL<<51) /* overflow disable (optional) */ -#define FPCR_INV (1UL<<52) /* invalid operation */ -#define FPCR_DZE (1UL<<53) /* division by zero */ -#define FPCR_OVF (1UL<<54) /* overflow */ -#define FPCR_UNF (1UL<<55) /* underflow */ -#define FPCR_INE (1UL<<56) /* inexact */ -#define FPCR_IOV (1UL<<57) /* integer overflow */ -#define FPCR_UNDZ (1UL<<60) /* underflow to zero (opt.) */ -#define FPCR_UNFD (1UL<<61) /* underflow disable (opt.) */ -#define FPCR_INED (1UL<<62) /* inexact disable (opt.) */ -#define FPCR_SUM (1UL<<63) /* summary bit */ - -#define FPCR_DYN_SHIFT 58 /* first dynamic rounding mode bit */ -#define FPCR_DYN_CHOPPED (0x0UL << FPCR_DYN_SHIFT) /* towards 0 */ -#define FPCR_DYN_MINUS (0x1UL << FPCR_DYN_SHIFT) /* towards -INF */ -#define FPCR_DYN_NORMAL (0x2UL << FPCR_DYN_SHIFT) /* towards nearest */ -#define FPCR_DYN_PLUS (0x3UL << FPCR_DYN_SHIFT) /* towards +INF */ -#define FPCR_DYN_MASK (0x3UL << FPCR_DYN_SHIFT) - -#define FPCR_MASK 0xffff800000000000L - -/* - * IEEE trap enables are implemented in software. These per-thread - * bits are stored in the "ieee_state" field of "struct thread_info". - * Thus, the bits are defined so as not to conflict with the - * floating-point enable bit (which is architected). On top of that, - * we want to make these bits compatible with OSF/1 so - * ieee_set_fp_control() etc. can be implemented easily and - * compatibly. The corresponding definitions are in - * /usr/include/machine/fpu.h under OSF/1. - */ -#define IEEE_TRAP_ENABLE_INV (1UL<<1) /* invalid op */ -#define IEEE_TRAP_ENABLE_DZE (1UL<<2) /* division by zero */ -#define IEEE_TRAP_ENABLE_OVF (1UL<<3) /* overflow */ -#define IEEE_TRAP_ENABLE_UNF (1UL<<4) /* underflow */ -#define IEEE_TRAP_ENABLE_INE (1UL<<5) /* inexact */ -#define IEEE_TRAP_ENABLE_DNO (1UL<<6) /* denorm */ -#define IEEE_TRAP_ENABLE_MASK (IEEE_TRAP_ENABLE_INV | IEEE_TRAP_ENABLE_DZE |\ - IEEE_TRAP_ENABLE_OVF | IEEE_TRAP_ENABLE_UNF |\ - IEEE_TRAP_ENABLE_INE | IEEE_TRAP_ENABLE_DNO) - -/* Denorm and Underflow flushing */ -#define IEEE_MAP_DMZ (1UL<<12) /* Map denorm inputs to zero */ -#define IEEE_MAP_UMZ (1UL<<13) /* Map underflowed outputs to zero */ - -#define IEEE_MAP_MASK (IEEE_MAP_DMZ | IEEE_MAP_UMZ) - -/* status bits coming from fpcr: */ -#define IEEE_STATUS_INV (1UL<<17) -#define IEEE_STATUS_DZE (1UL<<18) -#define IEEE_STATUS_OVF (1UL<<19) -#define IEEE_STATUS_UNF (1UL<<20) -#define IEEE_STATUS_INE (1UL<<21) -#define IEEE_STATUS_DNO (1UL<<22) - -#define IEEE_STATUS_MASK (IEEE_STATUS_INV | IEEE_STATUS_DZE | \ - IEEE_STATUS_OVF | IEEE_STATUS_UNF | \ - IEEE_STATUS_INE | IEEE_STATUS_DNO) - -#define IEEE_SW_MASK (IEEE_TRAP_ENABLE_MASK | \ - IEEE_STATUS_MASK | IEEE_MAP_MASK) - -#define IEEE_CURRENT_RM_SHIFT 32 -#define IEEE_CURRENT_RM_MASK (3UL<> 35) & IEEE_STATUS_MASK; - sw |= (fp >> 36) & IEEE_MAP_DMZ; - sw |= (~fp >> 48) & (IEEE_TRAP_ENABLE_INV - | IEEE_TRAP_ENABLE_DZE - | IEEE_TRAP_ENABLE_OVF); - sw |= (~fp >> 57) & (IEEE_TRAP_ENABLE_UNF | IEEE_TRAP_ENABLE_INE); - sw |= (fp >> 47) & IEEE_MAP_UMZ; - sw |= (~fp >> 41) & IEEE_TRAP_ENABLE_DNO; - return sw; -} - -#ifdef __KERNEL__ +#include /* The following two functions don't need trapb/excb instructions around the mf_fpcr/mt_fpcr instructions because (a) the kernel @@ -192,6 +72,4 @@ extern void alpha_write_fp_reg (unsigned long reg, unsigned long val); extern unsigned long alpha_read_fp_reg_s (unsigned long reg); extern void alpha_write_fp_reg_s (unsigned long reg, unsigned long val); -#endif /* __KERNEL__ */ - #endif /* __ASM_ALPHA_FPU_H */ -- cgit v1.2.3