From f3d549dd5b217d084c9fe6581e0430909440de2b Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 21 May 2012 16:05:45 -0600 Subject: dt: name all Tegra binding docs consistently Rename all Tegra binding documentation according to the first or primary compatible value they describe. This provides a clear naming scheme for the files, and prevents any naming conflicts should future SoC versions require their own binding. Signed-off-by: Stephen Warren --- Documentation/devicetree/bindings/spi/nvidia,tegra20-spi.txt | 5 +++++ Documentation/devicetree/bindings/spi/spi_nvidia.txt | 5 ----- 2 files changed, 5 insertions(+), 5 deletions(-) create mode 100644 Documentation/devicetree/bindings/spi/nvidia,tegra20-spi.txt delete mode 100644 Documentation/devicetree/bindings/spi/spi_nvidia.txt (limited to 'Documentation/devicetree/bindings/spi') diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-spi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-spi.txt new file mode 100644 index 00000000000..6b9e5189669 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-spi.txt @@ -0,0 +1,5 @@ +NVIDIA Tegra 2 SPI device + +Required properties: +- compatible : should be "nvidia,tegra20-spi". +- gpios : should specify GPIOs used for chipselect. diff --git a/Documentation/devicetree/bindings/spi/spi_nvidia.txt b/Documentation/devicetree/bindings/spi/spi_nvidia.txt deleted file mode 100644 index 6b9e5189669..00000000000 --- a/Documentation/devicetree/bindings/spi/spi_nvidia.txt +++ /dev/null @@ -1,5 +0,0 @@ -NVIDIA Tegra 2 SPI device - -Required properties: -- compatible : should be "nvidia,tegra20-spi". -- gpios : should specify GPIOs used for chipselect. -- cgit v1.2.3 From 2b90807549e5d1f700e523ddd098651ecfc18e65 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Fri, 13 Jul 2012 07:15:15 +0900 Subject: spi: s3c64xx: add device tree support Add support for device based discovery. Signed-off-by: Thomas Abraham Acked-by: Jaswinder Singh Acked-by: Grant Likely Signed-off-by: Kukjin Kim --- .../devicetree/bindings/spi/spi-samsung.txt | 113 +++++++++++++++++++++ 1 file changed, 113 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-samsung.txt (limited to 'Documentation/devicetree/bindings/spi') diff --git a/Documentation/devicetree/bindings/spi/spi-samsung.txt b/Documentation/devicetree/bindings/spi/spi-samsung.txt new file mode 100644 index 00000000000..59bfc4f9feb --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-samsung.txt @@ -0,0 +1,113 @@ +* Samsung SPI Controller + +The Samsung SPI controller is used to interface with various devices such as flash +and display controllers using the SPI communication interface. + +Required SoC Specific Properties: + +- compatible: should be one of the following. + - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms + - samsung,s3c6410-spi: for s3c6410 platforms + - samsung,s5p6440-spi: for s5p6440 and s5p6450 platforms + - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms + - samsung,exynos4210-spi: for exynos4 and exynos5 platforms + +- reg: physical base address of the controller and length of memory mapped + region. + +- interrupts: The interrupt number to the cpu. The interrupt specifier format + depends on the interrupt controller. + +- tx-dma-channel: The dma channel specifier for tx operations. The format of + the dma specifier depends on the dma controller. + +- rx-dma-channel: The dma channel specifier for rx operations. The format of + the dma specifier depends on the dma controller. + +Required Board Specific Properties: + +- #address-cells: should be 1. +- #size-cells: should be 0. +- gpios: The gpio specifier for clock, mosi and miso interface lines (in the + order specified). The format of the gpio specifier depends on the gpio + controller. + +Optional Board Specific Properties: + +- samsung,spi-src-clk: If the spi controller includes a internal clock mux to + select the clock source for the spi bus clock, this property can be used to + indicate the clock to be used for driving the spi bus clock. If not specified, + the clock number 0 is used as default. + +- num-cs: Specifies the number of chip select lines supported. If + not specified, the default number of chip select lines is set to 1. + +SPI Controller specific data in SPI slave nodes: + +- The spi slave nodes should provide the following information which is required + by the spi controller. + + - cs-gpio: A gpio specifier that specifies the gpio line used as + the slave select line by the spi controller. The format of the gpio + specifier depends on the gpio controller. + + - samsung,spi-feedback-delay: The sampling phase shift to be applied on the + miso line (to account for any lag in the miso line). The following are the + valid values. + + - 0: No phase shift. + - 1: 90 degree phase shift sampling. + - 2: 180 degree phase shift sampling. + - 3: 270 degree phase shift sampling. + +Aliases: + +- All the SPI controller nodes should be represented in the aliases node using + the following format 'spi{n}' where n is a unique number for the alias. + + +Example: + +- SoC Specific Portion: + + spi_0: spi@12d20000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x12d20000 0x100>; + interrupts = <0 66 0>; + tx-dma-channel = <&pdma0 5>; + rx-dma-channel = <&pdma0 4>; + }; + +- Board Specific Portion: + + spi_0: spi@12d20000 { + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpa2 4 2 3 0>, + <&gpa2 6 2 3 0>, + <&gpa2 7 2 3 0>; + + w25q80bw@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "w25x80"; + reg = <0>; + spi-max-frequency = <10000>; + + controller-data { + cs-gpio = <&gpa2 5 1 0 3>; + samsung,spi-feedback-delay = <0>; + }; + + partition@0 { + label = "U-Boot"; + reg = <0x0 0x40000>; + read-only; + }; + + partition@40000 { + label = "Kernel"; + reg = <0x40000 0xc0000>; + }; + }; + }; -- cgit v1.2.3 From 5d74c8a065abc8ae283a6fe8a1e7dd6313a22165 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 17 Jul 2012 23:13:06 +0200 Subject: ARM: EXYNOS: mark the DMA channel binding for SPI as preliminary Bindings for DMA channels are still under discussion and will change once this has been resolved. Therefore we mark them the newly added ones as preliminary. Let's hope nobody starts relying on them... Signed-off-by: Arnd Bergmann --- Documentation/devicetree/bindings/spi/spi-samsung.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree/bindings/spi') diff --git a/Documentation/devicetree/bindings/spi/spi-samsung.txt b/Documentation/devicetree/bindings/spi/spi-samsung.txt index 59bfc4f9feb..a15ffeddfba 100644 --- a/Documentation/devicetree/bindings/spi/spi-samsung.txt +++ b/Documentation/devicetree/bindings/spi/spi-samsung.txt @@ -18,6 +18,9 @@ Required SoC Specific Properties: - interrupts: The interrupt number to the cpu. The interrupt specifier format depends on the interrupt controller. +[PRELIMINARY: the dma channel allocation will change once there are +official DMA bindings] + - tx-dma-channel: The dma channel specifier for tx operations. The format of the dma specifier depends on the dma controller. -- cgit v1.2.3 From f814f9ac5a819542fdf6db97305db9da603c1eeb Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Mon, 23 Jul 2012 12:08:09 +0200 Subject: spi/orion: add device tree binding Signed-off-by: Michael Walle Signed-off-by: Andrew Lunn Acked-by: Jason Cooper Acked-by: Sebastian Hesselbarth Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-orion.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-orion.txt (limited to 'Documentation/devicetree/bindings/spi') diff --git a/Documentation/devicetree/bindings/spi/spi-orion.txt b/Documentation/devicetree/bindings/spi/spi-orion.txt new file mode 100644 index 00000000000..a3ff50fc76f --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-orion.txt @@ -0,0 +1,19 @@ +Marvell Orion SPI device + +Required properties: +- compatible : should be "marvell,orion-spi". +- reg : offset and length of the register set for the device +- cell-index : Which of multiple SPI controllers is this. +Optional properties: +- interrupts : Is currently not used. + +Example: + spi@10600 { + compatible = "marvell,orion-spi"; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + reg = <0x10600 0x28>; + interrupts = <23>; + status = "disabled"; + }; -- cgit v1.2.3 From 4ad1e5b5d1dde19f09e728ba8b5164968f9dabeb Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 3 Aug 2012 17:26:14 +0200 Subject: spi/mxs: Add SSP/SPI device tree documentation Signed-off-by: Marek Vasut Acked-by: Chris Ball Acked-by: Shawn Guo Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/mxs-spi.txt | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/mxs-spi.txt (limited to 'Documentation/devicetree/bindings/spi') diff --git a/Documentation/devicetree/bindings/spi/mxs-spi.txt b/Documentation/devicetree/bindings/spi/mxs-spi.txt new file mode 100644 index 00000000000..c36296f5ad2 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/mxs-spi.txt @@ -0,0 +1,18 @@ +* Freescale MX233/MX28 SSP/SPI + +Required properties: +- compatible: Should be "fsl,-spi", where soc is "imx23" or "imx28" +- reg: Offset and length of the register set for the device +- interrupts: Should contain SSP interrupts (error irq first, dma irq second) +- fsl,ssp-dma-channel: APBX DMA channel for the SSP + +Example: + +ssp0: ssp@80010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx28-spi"; + reg = <0x80010000 0x2000>; + interrupts = <96 82>; + fsl,ssp-dma-channel = <0>; +}; -- cgit v1.2.3 From 3ce8859e2e72713d3619285cab609d05c3591fc4 Mon Sep 17 00:00:00 2001 From: Guenter Roeck Date: Sat, 18 Aug 2012 09:06:27 -0700 Subject: spi: Master driver for NXP SC18IS602/603 This driver adds support for NXP SC18IS602/603 I2C to SPI bus bridge. Signed-off-by: Guenter Roeck Signed-off-by: Mark Brown --- .../devicetree/bindings/spi/spi-sc18is602.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-sc18is602.txt (limited to 'Documentation/devicetree/bindings/spi') diff --git a/Documentation/devicetree/bindings/spi/spi-sc18is602.txt b/Documentation/devicetree/bindings/spi/spi-sc18is602.txt new file mode 100644 index 00000000000..02f9033270a --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-sc18is602.txt @@ -0,0 +1,23 @@ +NXP SC18IS602/SCIS603 + +Required properties: + - compatible : Should be one of + "nxp,sc18is602" + "nxp,sc18is602b" + "nxp,sc18is603" + - reg: I2C bus address + +Optional properties: + - clock-frequency : external oscillator clock frequency. If not + specified, the SC18IS602 default frequency (7372000) will be used. + +The clock-frequency property is relevant and needed only if the chip has an +external oscillator (SC18IS603). + +Example: + + sc18is603@28 { + compatible = "nxp,sc18is603"; + reg = <0x28>; + clock-frequency = <14744000>; + } -- cgit v1.2.3 From 6d3952a7dfa80919842bbe01ac7f693d40a1eb84 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Wed, 22 Aug 2012 15:49:18 +0200 Subject: spi/pl022: Add devicetree support This patch adds device tree support to the spi-pl022 driver. Based on the initial patch by Alexandre Pereira da Silva Signed-off-by: Roland Stigge Acked-by: Alexandre Pereira da Silva Reviewed-by: Linus Walleij Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi_pl022.txt | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'Documentation/devicetree/bindings/spi') diff --git a/Documentation/devicetree/bindings/spi/spi_pl022.txt b/Documentation/devicetree/bindings/spi/spi_pl022.txt index 306ec3ff3c0..877f832c30a 100644 --- a/Documentation/devicetree/bindings/spi/spi_pl022.txt +++ b/Documentation/devicetree/bindings/spi/spi_pl022.txt @@ -6,7 +6,22 @@ Required properties: - interrupts : Should contain SPI controller interrupt Optional properties: +- num-cs : total number of chipselects - cs-gpios : should specify GPIOs used for chipselects. The gpios will be referred to as reg = in the SPI child nodes. If unspecified, a single SPI device without a chip select can be used. +SPI slave nodes must be children of the SPI master node and can +contain the following properties. + +- pl022,interface : interface type: + 0: SPI + 1: Texas Instruments Synchronous Serial Frame Format + 2: Microwire (Half Duplex) +- pl022,com-mode : polling, interrupt or dma +- pl022,rx-level-trig : Rx FIFO watermark level +- pl022,tx-level-trig : Tx FIFO watermark level +- pl022,ctrl-len : Microwire interface: Control length +- pl022,wait-state : Microwire interface: Wait state +- pl022,duplex : Microwire interface: Full/Half duplex + -- cgit v1.2.3 From 41962f90c605983fb04c23bab9c060c9f49ee4c3 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Wed, 22 Aug 2012 15:49:19 +0200 Subject: spi/dt: DT bindings documentation: "num-cs" property for SPI controllers Several SPI controller drivers have defined differently named properties for the number of chip selects. Now adding "num-cs" as a reference name for new bindings. Signed-off-by: Roland Stigge Reviewed-by: Linus Walleij Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-bus.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree/bindings/spi') diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt index e782add2e45..d2c33d0f533 100644 --- a/Documentation/devicetree/bindings/spi/spi-bus.txt +++ b/Documentation/devicetree/bindings/spi/spi-bus.txt @@ -21,6 +21,9 @@ assumption that board specific platform code will be used to manage chip selects. Individual drivers can define additional properties to support describing the chip select layout. +Optional property: +- num-cs : total number of chipselects + SPI slave nodes must be children of the SPI master node and can contain the following properties. - reg - (required) chip select address of device. -- cgit v1.2.3 From 6b52c00f2b4931c12117dc32a7cf6d5ee59f14ea Mon Sep 17 00:00:00 2001 From: David Daney Date: Wed, 22 Aug 2012 12:25:07 -0700 Subject: spi: Add SPI master controller for OCTEON SOCs. Add the driver, link it into the kbuild system and provide device tree binding documentation. Signed-off-by: David Daney Acked-by: Grant Likely Patchwork: http://patchwork.linux-mips.org/patch/4292/ Signed-off-by: John Crispin --- .../devicetree/bindings/spi/spi-octeon.txt | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-octeon.txt (limited to 'Documentation/devicetree/bindings/spi') diff --git a/Documentation/devicetree/bindings/spi/spi-octeon.txt b/Documentation/devicetree/bindings/spi/spi-octeon.txt new file mode 100644 index 00000000000..431add19234 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-octeon.txt @@ -0,0 +1,33 @@ +Cavium, Inc. OCTEON SOC SPI master controller. + +Required properties: +- compatible : "cavium,octeon-3010-spi" +- reg : The register base for the controller. +- interrupts : One interrupt, used by the controller. +- #address-cells : <1>, as required by generic SPI binding. +- #size-cells : <0>, also as required by generic SPI binding. + +Child nodes as per the generic SPI binding. + +Example: + + spi@1070000001000 { + compatible = "cavium,octeon-3010-spi"; + reg = <0x10700 0x00001000 0x0 0x100>; + interrupts = <0 58>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + compatible = "st,m95256", "atmel,at25"; + reg = <0>; + spi-max-frequency = <5000000>; + spi-cpha; + spi-cpol; + + pagesize = <64>; + size = <32768>; + address-width = <16>; + }; + }; + -- cgit v1.2.3 From 38ab18caa0ad9c844ba60f9618c5de6d6954da3e Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Wed, 5 Sep 2012 11:04:36 +0200 Subject: spi: spi-gpio: Add DT bindings This patch adds DT bindings to the spi-gpio driver and some documentation about how to use it. Signed-off-by: Daniel Mack Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-gpio.txt | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-gpio.txt (limited to 'Documentation/devicetree/bindings/spi') diff --git a/Documentation/devicetree/bindings/spi/spi-gpio.txt b/Documentation/devicetree/bindings/spi/spi-gpio.txt new file mode 100644 index 00000000000..8a824be1575 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-gpio.txt @@ -0,0 +1,29 @@ +SPI-GPIO devicetree bindings + +Required properties: + + - compatible: should be set to "spi-gpio" + - #address-cells: should be set to <0x1> + - ranges + - gpio-sck: GPIO spec for the SCK line to use + - gpio-miso: GPIO spec for the MISO line to use + - gpio-mosi: GPIO spec for the MOSI line to use + - cs-gpios: GPIOs to use for chipselect lines + - num-chipselects: number of chipselect lines + +Example: + + spi { + compatible = "spi-gpio"; + #address-cells = <0x1>; + ranges; + + gpio-sck = <&gpio 95 0>; + gpio-miso = <&gpio 98 0>; + gpio-mosi = <&gpio 97 0>; + cs-gpios = <&gpio 125 0>; + num-chipselects = <1>; + + /* clients */ + }; + -- cgit v1.2.3 From e64d07a2dae569fc3c938adac777562a1d6f151e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 22 Aug 2012 22:38:35 +0200 Subject: spi/mxs: Make the SPI block clock speed configurable via DT Add "clock-frequency" property, which allows configuring the SPI block's base speed. Signed-off-by: Marek Vasut Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/mxs-spi.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree/bindings/spi') diff --git a/Documentation/devicetree/bindings/spi/mxs-spi.txt b/Documentation/devicetree/bindings/spi/mxs-spi.txt index c36296f5ad2..e2e13957c2a 100644 --- a/Documentation/devicetree/bindings/spi/mxs-spi.txt +++ b/Documentation/devicetree/bindings/spi/mxs-spi.txt @@ -6,6 +6,10 @@ Required properties: - interrupts: Should contain SSP interrupts (error irq first, dma irq second) - fsl,ssp-dma-channel: APBX DMA channel for the SSP +Optional properties: +- clock-frequency : Input clock frequency to the SPI block in Hz. + Default is 160000000 Hz. + Example: ssp0: ssp@80010000 { -- cgit v1.2.3 From 39a6ac11df6579df0361922f05c43f0fac8daa37 Mon Sep 17 00:00:00 2001 From: Roland Stigge Date: Tue, 18 Sep 2012 15:53:53 +0200 Subject: spi/pl022: Devicetree support w/o platform data Even with devicetree support, we needed platform data to provide some data, leading to mixed device tree and platform data. This patch makes it possible to provide all that information via device tree. Now, the data must be provided via platform data _or_ device tree completely. Only in case of DMA where a callback specification is necessary (dma_filter()), platform data is the only option. Signed-off-by: Roland Stigge Acked-by: Arnd Bergmann Acked-by: Linus Walleij Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi_pl022.txt | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation/devicetree/bindings/spi') diff --git a/Documentation/devicetree/bindings/spi/spi_pl022.txt b/Documentation/devicetree/bindings/spi/spi_pl022.txt index 877f832c30a..f158fd31cfd 100644 --- a/Documentation/devicetree/bindings/spi/spi_pl022.txt +++ b/Documentation/devicetree/bindings/spi/spi_pl022.txt @@ -10,6 +10,13 @@ Optional properties: - cs-gpios : should specify GPIOs used for chipselects. The gpios will be referred to as reg = in the SPI child nodes. If unspecified, a single SPI device without a chip select can be used. +- pl022,autosuspend-delay : delay in ms following transfer completion before + the runtime power management system suspends the + device. A setting of 0 indicates no delay and the + device will be suspended immediately +- pl022,rt : indicates the controller should run the message pump with realtime + priority to minimise the transfer latency on the bus (boolean) + SPI slave nodes must be children of the SPI master node and can contain the following properties. -- cgit v1.2.3 From 0384e90b853357d24935c65ba0e1bdd27faa6e58 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Sun, 7 Oct 2012 18:19:44 +0200 Subject: spi/mcspi: allow configuration of pin directions Allow D0 to be an input and D1 to be an output, configurable via platform data and a new DT property. Based on a patch from Matus Ujhelyi Signed-off-by: Daniel Mack Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/omap-spi.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings/spi') diff --git a/Documentation/devicetree/bindings/spi/omap-spi.txt b/Documentation/devicetree/bindings/spi/omap-spi.txt index 81df374adbb..2ef0a6b8565 100644 --- a/Documentation/devicetree/bindings/spi/omap-spi.txt +++ b/Documentation/devicetree/bindings/spi/omap-spi.txt @@ -6,7 +6,9 @@ Required properties: - "ti,omap4-spi" for OMAP4+. - ti,spi-num-cs : Number of chipselect supported by the instance. - ti,hwmods: Name of the hwmod associated to the McSPI - +- ti,pindir-d0-in-d1-out: Select the D0 pin as input and D1 as + output. The default is D0 as output and + D1 as input. Example: -- cgit v1.2.3 From dc4dc36056392c0b0b1ca9e81bebff964b9297e0 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Tue, 30 Oct 2012 12:34:05 +0530 Subject: spi: tegra: add spi driver for SLINK controller Tegra20/Tegra30 supports the spi interface through its SLINK controller. Add spi driver for SLINK controller. Signed-off-by: Laxman Dewangan Reviewed-by: Stephen Warren Signed-off-by: Mark Brown --- .../bindings/spi/nvidia,tegra20-slink.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt (limited to 'Documentation/devicetree/bindings/spi') diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt new file mode 100644 index 00000000000..f5b1ad1a1ec --- /dev/null +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt @@ -0,0 +1,26 @@ +NVIDIA Tegra20/Tegra30 SLINK controller. + +Required properties: +- compatible : should be "nvidia,tegra20-slink", "nvidia,tegra30-slink". +- reg: Should contain SLINK registers location and length. +- interrupts: Should contain SLINK interrupts. +- nvidia,dma-request-selector : The Tegra DMA controller's phandle and + request selector for this SLINK controller. + +Recommended properties: +- spi-max-frequency: Definition as per + Documentation/devicetree/bindings/spi/spi-bus.txt + +Example: + +slink@7000d600 { + compatible = "nvidia,tegra20-slink"; + reg = <0x7000d600 0x200>; + interrupts = <0 82 0x04>; + nvidia,dma-request-selector = <&apbdma 16>; + spi-max-frequency = <25000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +}; + -- cgit v1.2.3 From 8528547bcc33622176a27963dc8a2513d116b832 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Wed, 14 Nov 2012 05:54:47 +0530 Subject: spi: tegra: add spi driver for sflash controller NVIDIA's Tegra20 have the SPI (SFLASH) controller to interface with spi flash device which is used for system boot. Add the spi driver for this controller. Signed-off-by: Laxman Dewangan Acked-by: Stephen Warren Tested-by: Stephen Warren Signed-off-by: Mark Brown --- .../bindings/spi/nvidia,tegra20-sflash.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt (limited to 'Documentation/devicetree/bindings/spi') diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt new file mode 100644 index 00000000000..8cf24f6f0a9 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt @@ -0,0 +1,26 @@ +NVIDIA Tegra20 SFLASH controller. + +Required properties: +- compatible : should be "nvidia,tegra20-sflash". +- reg: Should contain SFLASH registers location and length. +- interrupts: Should contain SFLASH interrupts. +- nvidia,dma-request-selector : The Tegra DMA controller's phandle and + request selector for this SFLASH controller. + +Recommended properties: +- spi-max-frequency: Definition as per + Documentation/devicetree/bindings/spi/spi-bus.txt + +Example: + +spi@7000d600 { + compatible = "nvidia,tegra20-sflash"; + reg = <0x7000c380 0x80>; + interrupts = <0 39 0x04>; + nvidia,dma-request-selector = <&apbdma 16>; + spi-max-frequency = <25000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +}; + -- cgit v1.2.3 From 2cd451792db174382aaca96c75bc3bf47a6065fe Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Wed, 14 Nov 2012 11:14:26 +0800 Subject: spi/omap: fix D0/D1 direction confusion 0384e90b8 ("spi/mcspi: allow configuration of pin directions") did what it claimed to do the wrong way around. D0/D1 is configured as output by *clearing* the bits in the conf registers, hence also breaking the former default behaviour. Fix this before that change is merged to mainline. Signed-off-by: Daniel Mack Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/omap-spi.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree/bindings/spi') diff --git a/Documentation/devicetree/bindings/spi/omap-spi.txt b/Documentation/devicetree/bindings/spi/omap-spi.txt index 2ef0a6b8565..938809c6829 100644 --- a/Documentation/devicetree/bindings/spi/omap-spi.txt +++ b/Documentation/devicetree/bindings/spi/omap-spi.txt @@ -6,9 +6,9 @@ Required properties: - "ti,omap4-spi" for OMAP4+. - ti,spi-num-cs : Number of chipselect supported by the instance. - ti,hwmods: Name of the hwmod associated to the McSPI -- ti,pindir-d0-in-d1-out: Select the D0 pin as input and D1 as - output. The default is D0 as output and - D1 as input. +- ti,pindir-d0-out-d1-in: Select the D0 pin as output and D1 as + input. The default is D0 as input and + D1 as output. Example: -- cgit v1.2.3 From 743179849015dc71bb2ea63d8cd4bfa7fdfb4bc6 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Thu, 15 Nov 2012 20:19:57 +0100 Subject: of_spi: add generic binding support to specify cs gpio This will allow to use gpio for chip select with no modification in the driver binding When use the cs-gpios, the gpio number will be passed via the cs_gpio field and the number of chip select will automatically increased with max(hw cs, gpio cs). So if for example the controller has 2 CS lines, and the cs-gpios property looks like this: cs-gpios = <&gpio1 0 0> <0> <&gpio1 1 0> <&gpio1 2 0>; Then it should be configured so that num_chipselect = 4 with the following mapping: cs0 : &gpio1 0 0 cs1 : native cs2 : &gpio1 1 0 cs3 : &gpio1 2 0 Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Cc: devicetree-discuss@lists.ozlabs.org Cc: spi-devel-general@lists.sourceforge.net Signed-off-by: Richard Genoud [grant.likely: fixed up type of cs count so min() can do type checking] Signed-off-by: Grant Likely --- Documentation/devicetree/bindings/spi/spi-bus.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'Documentation/devicetree/bindings/spi') diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt index d2c33d0f533..77a8b0d39b5 100644 --- a/Documentation/devicetree/bindings/spi/spi-bus.txt +++ b/Documentation/devicetree/bindings/spi/spi-bus.txt @@ -12,6 +12,7 @@ The SPI master node requires the following properties: - #size-cells - should be zero. - compatible - name of SPI bus controller following generic names recommended practice. +- cs-gpios - (optional) gpios chip select. No other properties are required in the SPI bus node. It is assumed that a driver for an SPI bus device will understand that it is an SPI bus. However, the binding does not attempt to define the specific method for @@ -24,6 +25,22 @@ support describing the chip select layout. Optional property: - num-cs : total number of chipselects +If cs-gpios is used the number of chip select will automatically increased +with max(cs-gpios > hw cs) + +So if for example the controller has 2 CS lines, and the cs-gpios +property looks like this: + +cs-gpios = <&gpio1 0 0> <0> <&gpio1 1 0> <&gpio1 2 0>; + +Then it should be configured so that num_chipselect = 4 with the +following mapping: + +cs0 : &gpio1 0 0 +cs1 : native +cs2 : &gpio1 1 0 +cs3 : &gpio1 2 0 + SPI slave nodes must be children of the SPI master node and can contain the following properties. - reg - (required) chip select address of device. @@ -37,6 +54,9 @@ contain the following properties. - spi-cs-high - (optional) Empty property indicating device requires chip select active high +If a gpio chipselect is used for the SPI slave the gpio number will be passed +via the cs_gpio + SPI example for an MPC5200 SPI bus: spi@f00 { #address-cells = <1>; -- cgit v1.2.3 From c20151dff8a6d503c0d0cc4387c33a618cdabcb7 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Thu, 6 Dec 2012 16:55:33 +0100 Subject: spi: Add support for specifying 3-wire mode via device tree This patch allows to specify that a SPI device is connected in 3-wire mode via device tree. Signed-off-by: Lars-Peter Clausen Acked-by: Rob Herring Signed-off-by: Grant Likely --- Documentation/devicetree/bindings/spi/spi-bus.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree/bindings/spi') diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt index 77a8b0d39b5..296015e3c63 100644 --- a/Documentation/devicetree/bindings/spi/spi-bus.txt +++ b/Documentation/devicetree/bindings/spi/spi-bus.txt @@ -53,6 +53,8 @@ contain the following properties. shifted clock phase (CPHA) mode - spi-cs-high - (optional) Empty property indicating device requires chip select active high +- spi-3wire - (optional) Empty property indicating device requires + 3-wire mode. If a gpio chipselect is used for the SPI slave the gpio number will be passed via the cs_gpio -- cgit v1.2.3 From 850a5b670af6293fcb1852af57567d19150ff638 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Fri, 23 Nov 2012 13:44:39 +0100 Subject: spi/atmel: add DT support Use the newly introduce cs-gpios dt support on atmel. We do not use the hardware cs as it's wired and has bugs and limitations. As the controller believes that only active-low devices/systems exists. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Acked-by: Nicolas Ferre Signed-off-by: Grant Likely --- .../devicetree/bindings/spi/spi_atmel.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi_atmel.txt (limited to 'Documentation/devicetree/bindings/spi') diff --git a/Documentation/devicetree/bindings/spi/spi_atmel.txt b/Documentation/devicetree/bindings/spi/spi_atmel.txt new file mode 100644 index 00000000000..07e04cdc0c9 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi_atmel.txt @@ -0,0 +1,26 @@ +Atmel SPI device + +Required properties: +- compatible : should be "atmel,at91rm9200-spi". +- reg: Address and length of the register set for the device +- interrupts: Should contain spi interrupt +- cs-gpios: chipselects + +Example: + +spi1: spi@fffcc000 { + compatible = "atmel,at91rm9200-spi"; + reg = <0xfffcc000 0x4000>; + interrupts = <13 4 5>; + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&pioB 3 0>; + status = "okay"; + + mmc-slot@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + gpios = <&pioC 4 0>; /* CD */ + spi-max-frequency = <25000000>; + }; +}; -- cgit v1.2.3 From 6a79131318dd6f71ec46e0af1daa581e695fd5ab Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Fri, 14 Dec 2012 11:05:12 -0800 Subject: spi: fix tegra SPI binding examples Fix name of slink binding and address of sflash example to make it self consistent. Signed-off-by: Allen Martin Signed-off-by: Grant Likely --- Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt | 2 +- Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree/bindings/spi') diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt index 8cf24f6f0a9..7b53da5cb75 100644 --- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt @@ -13,7 +13,7 @@ Recommended properties: Example: -spi@7000d600 { +spi@7000c380 { compatible = "nvidia,tegra20-sflash"; reg = <0x7000c380 0x80>; interrupts = <0 39 0x04>; diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt index f5b1ad1a1ec..eefe15e3d95 100644 --- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt @@ -13,7 +13,7 @@ Recommended properties: Example: -slink@7000d600 { +spi@7000d600 { compatible = "nvidia,tegra20-slink"; reg = <0x7000d600 0x200>; interrupts = <0 82 0x04>; -- cgit v1.2.3