From 736b1c9c957e38b80d2e36b2ed196fa1c07468bc Mon Sep 17 00:00:00 2001 From: David Daney Date: Thu, 5 Jul 2012 18:12:38 +0200 Subject: MIPS: Octeon: Add device tree source files. The two device tree files octeon_3xxx.dts and octeon_68xx.dts are trimmed by code in a subsequent patch to reflect the hardware actually present on the board. To this end several properties that are not part of the declared bindings are added to aid in trimming off unwanted nodes. Since the device tree and the code that trims it are bound into the kernel binary, these 'marker' properties never escape into the wild, and are purely an implementation detail of the kernel early boot process. This is done for backwards compatibility with existing boards (identified by a board type enumeration value by their bootloaders). New boards will always pass a device tree from the bootloader, the built-in trees are ignored in this case. Signed-off-by: David Daney Cc: linux-mips@linux-mips.org Cc: devicetree-discuss@lists.ozlabs.org Cc: Grant Likely Cc: Rob Herring Cc: linux-kernel@vger.kernel.org Cc: David Daney Patchwork: https://patchwork.linux-mips.org/patch/3937/ Signed-off-by: Ralf Baechle --- .../devicetree/bindings/mips/cavium/ciu2.txt | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/cavium/ciu2.txt (limited to 'Documentation/devicetree/bindings/mips/cavium/ciu2.txt') diff --git a/Documentation/devicetree/bindings/mips/cavium/ciu2.txt b/Documentation/devicetree/bindings/mips/cavium/ciu2.txt new file mode 100644 index 00000000000..0ec7ba8bbbc --- /dev/null +++ b/Documentation/devicetree/bindings/mips/cavium/ciu2.txt @@ -0,0 +1,27 @@ +* Central Interrupt Unit + +Properties: +- compatible: "cavium,octeon-6880-ciu2" + + Compatibility with 68XX SOCs. + +- interrupt-controller: This is an interrupt controller. + +- reg: The base address of the CIU's register bank. + +- #interrupt-cells: Must be <2>. The first cell is the bank within + the CIU and may have a value between 0 and 63. The second cell is + the bit within the bank and may also have a value between 0 and 63. + +Example: + interrupt-controller@1070100000000 { + compatible = "cavium,octeon-6880-ciu2"; + interrupt-controller; + /* Interrupts are specified by two parts: + * 1) Controller register (0..63) + * 2) Bit within the register (0..63) + */ + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x10701 0x00000000 0x0 0x4000000>; + }; -- cgit v1.2.3