Aurora Cache Controller was designed to be compatible with the ARM L2
Cache Controller. It comes with some difference or improvement such
- no cache id part number available through hardware (need to get it
by the DT).
- always write through mode available.
- two flavors of the controller outer cache and system cache (meaning
maintenance operations on L1 are broadcasted to the L2 and L2
performs the same operation).
- in outer cache mode, the cache maintenance operations are improved and
can be done on a range inside a page and are not limited to a cache
Tested-and-Reviewed-by: Lior Amsalem <firstname.lastname@example.org>
Signed-off-by: Gregory CLEMENT <email@example.com>
Signed-off-by: Yehuda Yitschak <firstname.lastname@example.org>
Reviewed-by: Will Deacon <email@example.com>
Signed-off-by: Russell King <firstname.lastname@example.org>