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-rw-r--r--arch/arm/mach-msm/platsmp.c34
1 files changed, 16 insertions, 18 deletions
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index db0117ec55f..7ed69b69c87 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -22,23 +22,14 @@
#include <asm/mach-types.h>
#include <asm/smp_plat.h>
-#include <mach/msm_iomap.h>
-
#include "scm-boot.h"
+#include "common.h"
#define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0
#define SCSS_CPU1CORE_RESET 0xD80
#define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64
-/* Mask for edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
-#define GIC_PPI_EDGE_MASK 0xFFFFD7FF
-
extern void msm_secondary_startup(void);
-/*
- * control for which core is the next to come out of the secondary
- * boot "holding pen".
- */
-volatile int pen_release = -1;
static DEFINE_SPINLOCK(boot_lock);
@@ -48,11 +39,8 @@ static inline int get_core_count(void)
return ((read_cpuid_id() >> 4) & 3) + 1;
}
-void __cpuinit platform_secondary_init(unsigned int cpu)
+static void __cpuinit msm_secondary_init(unsigned int cpu)
{
- /* Configure edge-triggered PPIs */
- writel(GIC_PPI_EDGE_MASK, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
-
/*
* if any interrupts are already enabled for the primary
* core (e.g. timer irq), then they will not have been enabled
@@ -93,7 +81,7 @@ static __cpuinit void prepare_cold_cpu(unsigned int cpu)
"address\n");
}
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int __cpuinit msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
static int cold_boot_done;
@@ -127,7 +115,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
* the boot monitor to read the system wide flags register,
* and branch to the address found there.
*/
- gic_raise_softirq(cpumask_of(cpu), 1);
+ gic_raise_softirq(cpumask_of(cpu), 0);
timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) {
@@ -153,7 +141,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
* does not support the ARM SCU, so just set the possible cpu mask to
* NR_CPUS.
*/
-void __init smp_init_cpus(void)
+static void __init msm_smp_init_cpus(void)
{
unsigned int i, ncores = get_core_count();
@@ -169,6 +157,16 @@ void __init smp_init_cpus(void)
set_smp_cross_call(gic_raise_softirq);
}
-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+static void __init msm_smp_prepare_cpus(unsigned int max_cpus)
{
}
+
+struct smp_operations msm_smp_ops __initdata = {
+ .smp_init_cpus = msm_smp_init_cpus,
+ .smp_prepare_cpus = msm_smp_prepare_cpus,
+ .smp_secondary_init = msm_secondary_init,
+ .smp_boot_secondary = msm_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+ .cpu_die = msm_cpu_die,
+#endif
+};