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-rw-r--r--arch/arm/mach-exynos/platsmp.c57
1 files changed, 40 insertions, 17 deletions
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 36c3984aaa4..c5c840e947b 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -32,17 +32,26 @@
#include <plat/cpu.h>
+#include "common.h"
+
extern void exynos4_secondary_startup(void);
-#define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
- S5P_INFORM5 : S5P_VA_SYSRAM)
+static inline void __iomem *cpu_boot_reg_base(void)
+{
+ if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
+ return S5P_INFORM5;
+ return S5P_VA_SYSRAM;
+}
-/*
- * control for which core is the next to come out of the secondary
- * boot "holding pen"
- */
+static inline void __iomem *cpu_boot_reg(int cpu)
+{
+ void __iomem *boot_reg;
-volatile int __cpuinitdata pen_release = -1;
+ boot_reg = cpu_boot_reg_base();
+ if (soc_is_exynos4412())
+ boot_reg += 4*cpu;
+ return boot_reg;
+}
/*
* Write pen_release in a way that is guaranteed to be visible to all
@@ -64,7 +73,7 @@ static void __iomem *scu_base_addr(void)
static DEFINE_SPINLOCK(boot_lock);
-void __cpuinit platform_secondary_init(unsigned int cpu)
+static void __cpuinit exynos_secondary_init(unsigned int cpu)
{
/*
* if any interrupts are already enabled for the primary
@@ -86,9 +95,10 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
spin_unlock(&boot_lock);
}
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
+ unsigned long phys_cpu = cpu_logical_map(cpu);
/*
* Set synchronisation state between this boot processor
@@ -104,7 +114,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
* Note that "pen_release" is the hardware CPU ID, whereas
* "cpu" is Linux's internal ID.
*/
- write_pen_release(cpu_logical_map(cpu));
+ write_pen_release(phys_cpu);
if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
__raw_writel(S5P_CORE_LOCAL_PWR_EN,
@@ -138,8 +148,8 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
smp_rmb();
__raw_writel(virt_to_phys(exynos4_secondary_startup),
- CPU1_BOOT_REG);
- gic_raise_softirq(cpumask_of(cpu), 1);
+ cpu_boot_reg(phys_cpu));
+ gic_raise_softirq(cpumask_of(cpu), 0);
if (pen_release == -1)
break;
@@ -161,7 +171,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
* which may be present or become present in the system.
*/
-void __init smp_init_cpus(void)
+static void __init exynos_smp_init_cpus(void)
{
void __iomem *scu_base = scu_base_addr();
unsigned int i, ncores;
@@ -184,9 +194,11 @@ void __init smp_init_cpus(void)
set_smp_cross_call(gic_raise_softirq);
}
-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
{
- if (!soc_is_exynos5250())
+ int i;
+
+ if (!(soc_is_exynos5250() || soc_is_exynos5440()))
scu_enable(scu_base_addr());
/*
@@ -195,6 +207,17 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
* until it receives a soft interrupt, and then the
* secondary CPU branches to this address.
*/
- __raw_writel(virt_to_phys(exynos4_secondary_startup),
- CPU1_BOOT_REG);
+ for (i = 1; i < max_cpus; ++i)
+ __raw_writel(virt_to_phys(exynos4_secondary_startup),
+ cpu_boot_reg(cpu_logical_map(i)));
}
+
+struct smp_operations exynos_smp_ops __initdata = {
+ .smp_init_cpus = exynos_smp_init_cpus,
+ .smp_prepare_cpus = exynos_smp_prepare_cpus,
+ .smp_secondary_init = exynos_secondary_init,
+ .smp_boot_secondary = exynos_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+ .cpu_die = exynos_cpu_die,
+#endif
+};