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-rw-r--r--arch/arm/include/asm/fpstate.h2
-rw-r--r--arch/arm/include/asm/glue-cache.h2
-rw-r--r--arch/arm/include/asm/glue.h4
-rw-r--r--arch/arm/include/asm/hardware/pl080.h2
-rw-r--r--arch/arm/include/asm/system.h2
-rw-r--r--arch/arm/include/asm/ucontext.h2
6 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/include/asm/fpstate.h b/arch/arm/include/asm/fpstate.h
index ee5e03efc1b..3ad4c10d0d8 100644
--- a/arch/arm/include/asm/fpstate.h
+++ b/arch/arm/include/asm/fpstate.h
@@ -18,7 +18,7 @@
* VFP storage area has:
* - FPEXC, FPSCR, FPINST and FPINST2.
* - 16 or 32 double precision data registers
- * - an implementation-dependant word of state for FLDMX/FSTMX (pre-ARMv6)
+ * - an implementation-dependent word of state for FLDMX/FSTMX (pre-ARMv6)
*
* FPEXC will always be non-zero once the VFP has been used in this process.
*/
diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h
index c7afbc552c7..7e30874377e 100644
--- a/arch/arm/include/asm/glue-cache.h
+++ b/arch/arm/include/asm/glue-cache.h
@@ -126,7 +126,7 @@
#endif
#if !defined(_CACHE) && !defined(MULTI_CACHE)
-#error Unknown cache maintainence model
+#error Unknown cache maintenance model
#endif
#ifndef MULTI_CACHE
diff --git a/arch/arm/include/asm/glue.h b/arch/arm/include/asm/glue.h
index 0ec35d1698a..fbf71d75ec8 100644
--- a/arch/arm/include/asm/glue.h
+++ b/arch/arm/include/asm/glue.h
@@ -10,8 +10,8 @@
*
* This file provides the glue to stick the processor-specific bits
* into the kernel in an efficient manner. The idea is to use branches
- * when we're only targetting one class of TLB, or indirect calls
- * when we're targetting multiple classes of TLBs.
+ * when we're only targeting one class of TLB, or indirect calls
+ * when we're targeting multiple classes of TLBs.
*/
#ifdef __KERNEL__
diff --git a/arch/arm/include/asm/hardware/pl080.h b/arch/arm/include/asm/hardware/pl080.h
index f35b86e68dd..e4a04e4e562 100644
--- a/arch/arm/include/asm/hardware/pl080.h
+++ b/arch/arm/include/asm/hardware/pl080.h
@@ -16,7 +16,7 @@
* make it not entierly compatible with the PL080 specification from
* ARM. When in doubt, check the Samsung documentation first.
*
- * The Samsung defines are PL080S, and add an extra controll register,
+ * The Samsung defines are PL080S, and add an extra control register,
* the ability to move more than 2^11 counts of data and some extra
* OneNAND features.
*/
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 9a87823642d..885be097769 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -249,7 +249,7 @@ do { \
* cache totally. This means that the cache becomes inconsistent, and,
* since we use normal loads/stores as well, this is really bad.
* Typically, this causes oopsen in filp_close, but could have other,
- * more disasterous effects. There are two work-arounds:
+ * more disastrous effects. There are two work-arounds:
* 1. Disable interrupts and emulate the atomic swap
* 2. Clean the cache, perform atomic swap, flush the cache
*
diff --git a/arch/arm/include/asm/ucontext.h b/arch/arm/include/asm/ucontext.h
index 47f023aa849..14749aec94b 100644
--- a/arch/arm/include/asm/ucontext.h
+++ b/arch/arm/include/asm/ucontext.h
@@ -47,7 +47,7 @@ struct crunch_sigframe {
#endif
#ifdef CONFIG_IWMMXT
-/* iwmmxt_area is 0x98 bytes long, preceeded by 8 bytes of signature */
+/* iwmmxt_area is 0x98 bytes long, preceded by 8 bytes of signature */
#define IWMMXT_MAGIC 0x12ef842a
#define IWMMXT_STORAGE_SIZE (IWMMXT_SIZE + 8)