ARM: OMAP2+: Move iommu2 to drivers/iommu/omap-iommu2.c
This file should not be in arch/arm. Move it to drivers/iommu to allow making most of the header local to drivers/iommu. This is needed as we are removing plat and mach includes from drivers for ARM common zImage support. Cc: Ido Yariv <ido@wizery.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Mauro Carvalho Chehab <mchehab@infradead.org> Cc: Omar Ramirez Luna <omar.luna@linaro.org> Cc: linux-media@vger.kernel.org Acked-by: Ohad Ben-Cohen <ohad@wizery.com> Acked-by: Joerg Roedel <joro@8bytes.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tony Lindgren
parent
c8d35c84f5
commit
ed1c7de29f
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@ -184,8 +184,6 @@ obj-$(CONFIG_HW_PERF_EVENTS) += pmu.o
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obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
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mailbox_mach-objs := mailbox.o
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obj-$(CONFIG_OMAP_IOMMU) += iommu2.o
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iommu-$(CONFIG_OMAP_IOMMU) := omap-iommu.o
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obj-y += $(iommu-m) $(iommu-y)
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@ -10,103 +10,21 @@
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* published by the Free Software Foundation.
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*/
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#ifndef __MACH_IOMMU_H
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#define __MACH_IOMMU_H
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#define MMU_REG_SIZE 256
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#include <linux/io.h>
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#if defined(CONFIG_ARCH_OMAP1)
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#error "iommu for this processor not implemented yet"
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#endif
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struct iotlb_entry {
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u32 da;
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u32 pa;
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u32 pgsz, prsvd, valid;
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union {
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u16 ap;
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struct {
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u32 endian, elsz, mixed;
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};
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};
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};
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struct omap_iommu {
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const char *name;
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struct module *owner;
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struct clk *clk;
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void __iomem *regbase;
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struct device *dev;
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void *isr_priv;
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struct iommu_domain *domain;
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unsigned int refcount;
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spinlock_t iommu_lock; /* global for this whole object */
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/*
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* We don't change iopgd for a situation like pgd for a task,
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* but share it globally for each iommu.
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*/
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u32 *iopgd;
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spinlock_t page_table_lock; /* protect iopgd */
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int nr_tlb_entries;
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struct list_head mmap;
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struct mutex mmap_lock; /* protect mmap */
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void *ctx; /* iommu context: registres saved area */
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u32 da_start;
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u32 da_end;
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};
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struct cr_regs {
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union {
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struct {
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u16 cam_l;
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u16 cam_h;
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};
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u32 cam;
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};
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union {
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struct {
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u16 ram_l;
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u16 ram_h;
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};
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u32 ram;
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};
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};
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struct iotlb_lock {
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short base;
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short vict;
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};
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/* architecture specific functions */
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struct iommu_functions {
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unsigned long version;
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int (*enable)(struct omap_iommu *obj);
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void (*disable)(struct omap_iommu *obj);
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void (*set_twl)(struct omap_iommu *obj, bool on);
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u32 (*fault_isr)(struct omap_iommu *obj, u32 *ra);
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void (*tlb_read_cr)(struct omap_iommu *obj, struct cr_regs *cr);
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void (*tlb_load_cr)(struct omap_iommu *obj, struct cr_regs *cr);
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struct cr_regs *(*alloc_cr)(struct omap_iommu *obj,
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struct iotlb_entry *e);
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int (*cr_valid)(struct cr_regs *cr);
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u32 (*cr_to_virt)(struct cr_regs *cr);
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void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e);
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ssize_t (*dump_cr)(struct omap_iommu *obj, struct cr_regs *cr,
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char *buf);
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u32 (*get_pte_attr)(struct iotlb_entry *e);
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void (*save_ctx)(struct omap_iommu *obj);
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void (*restore_ctx)(struct omap_iommu *obj);
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ssize_t (*dump_ctx)(struct omap_iommu *obj, char *buf, ssize_t len);
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/**
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* struct iommu_arch_data - omap iommu private data
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* @name: name of the iommu device
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* @iommu_dev: handle of the iommu device
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*
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* This is an omap iommu private data object, which binds an iommu user
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* to its iommu device. This object should be placed at the iommu user's
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* dev_archdata so generic IOMMU API can be used without having to
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* utilize omap-specific plumbing anymore.
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*/
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struct omap_iommu_arch_data {
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const char *name;
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struct omap_iommu *iommu_dev;
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};
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/**
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@ -129,165 +47,3 @@ struct iommu_platform_data {
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u32 da_start;
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u32 da_end;
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};
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/**
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* struct iommu_arch_data - omap iommu private data
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* @name: name of the iommu device
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* @iommu_dev: handle of the iommu device
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*
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* This is an omap iommu private data object, which binds an iommu user
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* to its iommu device. This object should be placed at the iommu user's
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* dev_archdata so generic IOMMU API can be used without having to
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* utilize omap-specific plumbing anymore.
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*/
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struct omap_iommu_arch_data {
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const char *name;
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struct omap_iommu *iommu_dev;
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};
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#ifdef CONFIG_IOMMU_API
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/**
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* dev_to_omap_iommu() - retrieves an omap iommu object from a user device
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* @dev: iommu client device
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*/
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static inline struct omap_iommu *dev_to_omap_iommu(struct device *dev)
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{
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struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
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return arch_data->iommu_dev;
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}
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#endif
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/* IOMMU errors */
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#define OMAP_IOMMU_ERR_TLB_MISS (1 << 0)
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#define OMAP_IOMMU_ERR_TRANS_FAULT (1 << 1)
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#define OMAP_IOMMU_ERR_EMU_MISS (1 << 2)
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#define OMAP_IOMMU_ERR_TBLWALK_FAULT (1 << 3)
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#define OMAP_IOMMU_ERR_MULTIHIT_FAULT (1 << 4)
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/*
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* MMU Register offsets
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*/
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#define MMU_REVISION 0x00
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#define MMU_SYSCONFIG 0x10
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#define MMU_SYSSTATUS 0x14
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#define MMU_IRQSTATUS 0x18
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#define MMU_IRQENABLE 0x1c
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#define MMU_WALKING_ST 0x40
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#define MMU_CNTL 0x44
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#define MMU_FAULT_AD 0x48
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#define MMU_TTB 0x4c
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#define MMU_LOCK 0x50
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#define MMU_LD_TLB 0x54
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#define MMU_CAM 0x58
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#define MMU_RAM 0x5c
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#define MMU_GFLUSH 0x60
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#define MMU_FLUSH_ENTRY 0x64
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#define MMU_READ_CAM 0x68
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#define MMU_READ_RAM 0x6c
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#define MMU_EMU_FAULT_AD 0x70
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#define MMU_REG_SIZE 256
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/*
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* MMU Register bit definitions
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*/
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#define MMU_LOCK_BASE_SHIFT 10
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#define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT)
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#define MMU_LOCK_BASE(x) \
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((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
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#define MMU_LOCK_VICT_SHIFT 4
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#define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT)
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#define MMU_LOCK_VICT(x) \
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((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
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#define MMU_CAM_VATAG_SHIFT 12
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#define MMU_CAM_VATAG_MASK \
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((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
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#define MMU_CAM_P (1 << 3)
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#define MMU_CAM_V (1 << 2)
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#define MMU_CAM_PGSZ_MASK 3
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#define MMU_CAM_PGSZ_1M (0 << 0)
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#define MMU_CAM_PGSZ_64K (1 << 0)
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#define MMU_CAM_PGSZ_4K (2 << 0)
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#define MMU_CAM_PGSZ_16M (3 << 0)
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#define MMU_RAM_PADDR_SHIFT 12
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#define MMU_RAM_PADDR_MASK \
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((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
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#define MMU_RAM_ENDIAN_MASK (1 << MMU_RAM_ENDIAN_SHIFT)
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#define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT)
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#define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT)
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#define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT)
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#define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT)
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#define MMU_RAM_MIXED_SHIFT 6
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#define MMU_RAM_MIXED_MASK (1 << MMU_RAM_MIXED_SHIFT)
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#define MMU_RAM_MIXED MMU_RAM_MIXED_MASK
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/*
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* utilities for super page(16MB, 1MB, 64KB and 4KB)
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*/
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#define iopgsz_max(bytes) \
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(((bytes) >= SZ_16M) ? SZ_16M : \
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((bytes) >= SZ_1M) ? SZ_1M : \
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((bytes) >= SZ_64K) ? SZ_64K : \
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((bytes) >= SZ_4K) ? SZ_4K : 0)
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#define bytes_to_iopgsz(bytes) \
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(((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \
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((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \
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((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \
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((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1)
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#define iopgsz_to_bytes(iopgsz) \
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(((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \
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((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \
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((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \
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((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0)
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#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
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/*
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* global functions
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*/
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extern u32 omap_iommu_arch_version(void);
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extern void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e);
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extern int
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omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e);
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extern int omap_iommu_set_isr(const char *name,
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int (*isr)(struct omap_iommu *obj, u32 da, u32 iommu_errs,
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void *priv),
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void *isr_priv);
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extern int omap_install_iommu_arch(const struct iommu_functions *ops);
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extern void omap_uninstall_iommu_arch(const struct iommu_functions *ops);
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extern int omap_foreach_iommu_device(void *data,
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int (*fn)(struct device *, void *));
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extern ssize_t
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omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len);
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extern size_t
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omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t len);
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/*
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* register accessors
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*/
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static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs)
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{
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return __raw_readl(obj->regbase + offs);
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}
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static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs)
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{
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__raw_writel(val, obj->regbase + offs);
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}
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#endif /* __MACH_IOMMU_H */
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@ -7,6 +7,7 @@ obj-$(CONFIG_DMAR_TABLE) += dmar.o
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obj-$(CONFIG_INTEL_IOMMU) += iova.o intel-iommu.o
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obj-$(CONFIG_IRQ_REMAP) += intel_irq_remapping.o irq_remapping.o
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obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o
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obj-$(CONFIG_OMAP_IOMMU) += omap-iommu2.o
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obj-$(CONFIG_OMAP_IOVMM) += omap-iovmm.o
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obj-$(CONFIG_OMAP_IOMMU_DEBUG) += omap-iommu-debug.o
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obj-$(CONFIG_TEGRA_IOMMU_GART) += tegra-gart.o
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@ -23,6 +23,7 @@
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#include <plat/iommu.h>
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#include "omap-iopgtable.h"
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#include "omap-iommu.h"
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#define MAXCOLUMN 100 /* for short messages */
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@ -22,12 +22,14 @@
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#include <linux/omap-iommu.h>
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#include <linux/mutex.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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#include <plat/iommu.h>
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#include "omap-iopgtable.h"
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#include "omap-iommu.h"
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#define for_each_iotlb_cr(obj, n, __i, cr) \
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for (__i = 0; \
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@ -1016,6 +1018,23 @@ static void iopte_cachep_ctor(void *iopte)
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clean_dcache_area(iopte, IOPTE_TABLE_SIZE);
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}
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static u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa,
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u32 flags)
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{
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memset(e, 0, sizeof(*e));
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e->da = da;
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e->pa = pa;
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e->valid = 1;
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/* FIXME: add OMAP1 support */
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e->pgsz = flags & MMU_CAM_PGSZ_MASK;
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e->endian = flags & MMU_RAM_ENDIAN_MASK;
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e->elsz = flags & MMU_RAM_ELSZ_MASK;
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e->mixed = flags & MMU_RAM_MIXED_MASK;
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return iopgsz_to_bytes(e->pgsz);
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}
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static int omap_iommu_map(struct iommu_domain *domain, unsigned long da,
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phys_addr_t pa, size_t bytes, int prot)
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{
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@ -0,0 +1,255 @@
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/*
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* omap iommu: main structures
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*
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* Copyright (C) 2008-2009 Nokia Corporation
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*
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* Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#if defined(CONFIG_ARCH_OMAP1)
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#error "iommu for this processor not implemented yet"
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#endif
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struct iotlb_entry {
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u32 da;
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u32 pa;
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u32 pgsz, prsvd, valid;
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union {
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u16 ap;
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struct {
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u32 endian, elsz, mixed;
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};
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};
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};
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struct omap_iommu {
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const char *name;
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struct module *owner;
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struct clk *clk;
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void __iomem *regbase;
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struct device *dev;
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void *isr_priv;
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struct iommu_domain *domain;
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unsigned int refcount;
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spinlock_t iommu_lock; /* global for this whole object */
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/*
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* We don't change iopgd for a situation like pgd for a task,
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* but share it globally for each iommu.
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*/
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u32 *iopgd;
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spinlock_t page_table_lock; /* protect iopgd */
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int nr_tlb_entries;
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struct list_head mmap;
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struct mutex mmap_lock; /* protect mmap */
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void *ctx; /* iommu context: registres saved area */
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u32 da_start;
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u32 da_end;
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};
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struct cr_regs {
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union {
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struct {
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u16 cam_l;
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u16 cam_h;
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};
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u32 cam;
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};
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union {
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struct {
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u16 ram_l;
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u16 ram_h;
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};
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u32 ram;
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};
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};
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struct iotlb_lock {
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short base;
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short vict;
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};
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/* architecture specific functions */
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struct iommu_functions {
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unsigned long version;
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int (*enable)(struct omap_iommu *obj);
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void (*disable)(struct omap_iommu *obj);
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void (*set_twl)(struct omap_iommu *obj, bool on);
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u32 (*fault_isr)(struct omap_iommu *obj, u32 *ra);
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void (*tlb_read_cr)(struct omap_iommu *obj, struct cr_regs *cr);
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void (*tlb_load_cr)(struct omap_iommu *obj, struct cr_regs *cr);
|
||||
|
||||
struct cr_regs *(*alloc_cr)(struct omap_iommu *obj,
|
||||
struct iotlb_entry *e);
|
||||
int (*cr_valid)(struct cr_regs *cr);
|
||||
u32 (*cr_to_virt)(struct cr_regs *cr);
|
||||
void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e);
|
||||
ssize_t (*dump_cr)(struct omap_iommu *obj, struct cr_regs *cr,
|
||||
char *buf);
|
||||
|
||||
u32 (*get_pte_attr)(struct iotlb_entry *e);
|
||||
|
||||
void (*save_ctx)(struct omap_iommu *obj);
|
||||
void (*restore_ctx)(struct omap_iommu *obj);
|
||||
ssize_t (*dump_ctx)(struct omap_iommu *obj, char *buf, ssize_t len);
|
||||
};
|
||||
|
||||
#ifdef CONFIG_IOMMU_API
|
||||
/**
|
||||
* dev_to_omap_iommu() - retrieves an omap iommu object from a user device
|
||||
* @dev: iommu client device
|
||||
*/
|
||||
static inline struct omap_iommu *dev_to_omap_iommu(struct device *dev)
|
||||
{
|
||||
struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
|
||||
|
||||
return arch_data->iommu_dev;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* IOMMU errors */
|
||||
#define OMAP_IOMMU_ERR_TLB_MISS (1 << 0)
|
||||
#define OMAP_IOMMU_ERR_TRANS_FAULT (1 << 1)
|
||||
#define OMAP_IOMMU_ERR_EMU_MISS (1 << 2)
|
||||
#define OMAP_IOMMU_ERR_TBLWALK_FAULT (1 << 3)
|
||||
#define OMAP_IOMMU_ERR_MULTIHIT_FAULT (1 << 4)
|
||||
|
||||
/*
|
||||
* MMU Register offsets
|
||||
*/
|
||||
#define MMU_REVISION 0x00
|
||||
#define MMU_SYSCONFIG 0x10
|
||||
#define MMU_SYSSTATUS 0x14
|
||||
#define MMU_IRQSTATUS 0x18
|
||||
#define MMU_IRQENABLE 0x1c
|
||||
#define MMU_WALKING_ST 0x40
|
||||
#define MMU_CNTL 0x44
|
||||
#define MMU_FAULT_AD 0x48
|
||||
#define MMU_TTB 0x4c
|
||||
#define MMU_LOCK 0x50
|
||||
#define MMU_LD_TLB 0x54
|
||||
#define MMU_CAM 0x58
|
||||
#define MMU_RAM 0x5c
|
||||
#define MMU_GFLUSH 0x60
|
||||
#define MMU_FLUSH_ENTRY 0x64
|
||||
#define MMU_READ_CAM 0x68
|
||||
#define MMU_READ_RAM 0x6c
|
||||
#define MMU_EMU_FAULT_AD 0x70
|
||||
|
||||
#define MMU_REG_SIZE 256
|
||||
|
||||
/*
|
||||
* MMU Register bit definitions
|
||||
*/
|
||||
#define MMU_LOCK_BASE_SHIFT 10
|
||||
#define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT)
|
||||
#define MMU_LOCK_BASE(x) \
|
||||
((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
|
||||
|
||||
#define MMU_LOCK_VICT_SHIFT 4
|
||||
#define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT)
|
||||
#define MMU_LOCK_VICT(x) \
|
||||
((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
|
||||
|
||||
#define MMU_CAM_VATAG_SHIFT 12
|
||||
#define MMU_CAM_VATAG_MASK \
|
||||
((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
|
||||
#define MMU_CAM_P (1 << 3)
|
||||
#define MMU_CAM_V (1 << 2)
|
||||
#define MMU_CAM_PGSZ_MASK 3
|
||||
#define MMU_CAM_PGSZ_1M (0 << 0)
|
||||
#define MMU_CAM_PGSZ_64K (1 << 0)
|
||||
#define MMU_CAM_PGSZ_4K (2 << 0)
|
||||
#define MMU_CAM_PGSZ_16M (3 << 0)
|
||||
|
||||
#define MMU_RAM_PADDR_SHIFT 12
|
||||
#define MMU_RAM_PADDR_MASK \
|
||||
((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
|
||||
|
||||
#define MMU_RAM_ENDIAN_MASK (1 << MMU_RAM_ENDIAN_SHIFT)
|
||||
#define MMU_RAM_ENDIAN_BIG (1 << MMU_RAM_ENDIAN_SHIFT)
|
||||
|
||||
#define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT)
|
||||
#define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT)
|
||||
#define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT)
|
||||
#define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT)
|
||||
#define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT)
|
||||
#define MMU_RAM_MIXED_SHIFT 6
|
||||
#define MMU_RAM_MIXED_MASK (1 << MMU_RAM_MIXED_SHIFT)
|
||||
#define MMU_RAM_MIXED MMU_RAM_MIXED_MASK
|
||||
|
||||
/*
|
||||
* utilities for super page(16MB, 1MB, 64KB and 4KB)
|
||||
*/
|
||||
|
||||
#define iopgsz_max(bytes) \
|
||||
(((bytes) >= SZ_16M) ? SZ_16M : \
|
||||
((bytes) >= SZ_1M) ? SZ_1M : \
|
||||
((bytes) >= SZ_64K) ? SZ_64K : \
|
||||
((bytes) >= SZ_4K) ? SZ_4K : 0)
|
||||
|
||||
#define bytes_to_iopgsz(bytes) \
|
||||
(((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \
|
||||
((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \
|
||||
((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \
|
||||
((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1)
|
||||
|
||||
#define iopgsz_to_bytes(iopgsz) \
|
||||
(((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \
|
||||
((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \
|
||||
((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \
|
||||
((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0)
|
||||
|
||||
#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
|
||||
|
||||
/*
|
||||
* global functions
|
||||
*/
|
||||
extern u32 omap_iommu_arch_version(void);
|
||||
|
||||
extern void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e);
|
||||
|
||||
extern int
|
||||
omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e);
|
||||
|
||||
extern int omap_iommu_set_isr(const char *name,
|
||||
int (*isr)(struct omap_iommu *obj, u32 da, u32 iommu_errs,
|
||||
void *priv),
|
||||
void *isr_priv);
|
||||
|
||||
extern void omap_iommu_save_ctx(struct device *dev);
|
||||
extern void omap_iommu_restore_ctx(struct device *dev);
|
||||
|
||||
extern int omap_install_iommu_arch(const struct iommu_functions *ops);
|
||||
extern void omap_uninstall_iommu_arch(const struct iommu_functions *ops);
|
||||
|
||||
extern int omap_foreach_iommu_device(void *data,
|
||||
int (*fn)(struct device *, void *));
|
||||
|
||||
extern ssize_t
|
||||
omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len);
|
||||
extern size_t
|
||||
omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t len);
|
||||
|
||||
/*
|
||||
* register accessors
|
||||
*/
|
||||
static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs)
|
||||
{
|
||||
return __raw_readl(obj->regbase + offs);
|
||||
}
|
||||
|
||||
static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs)
|
||||
{
|
||||
__raw_writel(val, obj->regbase + offs);
|
||||
}
|
||||
|
|
@ -13,6 +13,7 @@
|
|||
|
||||
#include <linux/err.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/jiffies.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/omap-iommu.h>
|
||||
|
|
@ -20,6 +21,7 @@
|
|||
#include <linux/stringify.h>
|
||||
|
||||
#include <plat/iommu.h>
|
||||
#include "omap-iommu.h"
|
||||
|
||||
/*
|
||||
* omap2 architecture specific register bit definitions
|
||||
|
|
@ -10,9 +10,6 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __PLAT_OMAP_IOMMU_H
|
||||
#define __PLAT_OMAP_IOMMU_H
|
||||
|
||||
/*
|
||||
* "L2 table" address mask and size definitions.
|
||||
*/
|
||||
|
|
@ -97,24 +94,5 @@ static inline phys_addr_t omap_iommu_translate(u32 d, u32 va, u32 mask)
|
|||
#define iopte_index(da) (((da) >> IOPTE_SHIFT) & (PTRS_PER_IOPTE - 1))
|
||||
#define iopte_offset(iopgd, da) (iopgd_page_vaddr(iopgd) + iopte_index(da))
|
||||
|
||||
static inline u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa,
|
||||
u32 flags)
|
||||
{
|
||||
memset(e, 0, sizeof(*e));
|
||||
|
||||
e->da = da;
|
||||
e->pa = pa;
|
||||
e->valid = 1;
|
||||
/* FIXME: add OMAP1 support */
|
||||
e->pgsz = flags & MMU_CAM_PGSZ_MASK;
|
||||
e->endian = flags & MMU_RAM_ENDIAN_MASK;
|
||||
e->elsz = flags & MMU_RAM_ELSZ_MASK;
|
||||
e->mixed = flags & MMU_RAM_MIXED_MASK;
|
||||
|
||||
return iopgsz_to_bytes(e->pgsz);
|
||||
}
|
||||
|
||||
#define to_iommu(dev) \
|
||||
(struct omap_iommu *)platform_get_drvdata(to_platform_device(dev))
|
||||
|
||||
#endif /* __PLAT_OMAP_IOMMU_H */
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@
|
|||
#include <plat/iommu.h>
|
||||
|
||||
#include "omap-iopgtable.h"
|
||||
#include "omap-iommu.h"
|
||||
|
||||
/*
|
||||
* IOVMF_FLAGS: attribute for iommu virtual memory area(iovma)
|
||||
|
|
|
|||
Reference in New Issue