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authorMohammed Shafi Shajakhan <mshajakhan@atheros.com>2011-06-17 11:07:32 +0530
committerJohn W. Linville <linville@tuxdriver.com>2011-06-20 15:34:18 -0400
commit81dc67601a49d1bfcfa85f644b14a013fc59e0ef (patch)
treee88545179b1dd6fb591d8e102f3e448a3f30d662 /drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
parent77572fd13d7f468216b85e68a006000726a59e89 (diff)
ath9k: Fix a corner case failure in sending PAPRD frames in HT40
when the AP is configured with HT40/2.4GHz and when PAPRD is enabled in station we have PAPRD training frames never sent out because of the following failure "PAPRD target power delta out of range". This consistently happens in channel 10,11 in Over The Air testing and rarely in channel 6 under wired setup. the reason behind this issue is all the HT40 rates target power are 0 when we operate in channel 10/11 at 2.4GHz Signed-off-by: Mohammed Shafi Shajakhan <mshajakhan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ar9003_eeprom.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_eeprom.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
index ff8150e46f0..2e370c668d4 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
@@ -1461,7 +1461,7 @@ static const struct ar9300_eeprom ar9300_h112 = {
{ { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
{ { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
- { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
+ { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
{ { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
{ { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
@@ -2616,7 +2616,7 @@ static const struct ar9300_eeprom ar9300_h116 = {
{ { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
{ { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
- { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
+ { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
{ { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
{ { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },