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authorJohn Fastabend <john.r.fastabend@intel.com>2011-04-26 07:25:58 +0000
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-06-21 01:19:27 -0700
commit72a32f1f3f68b7d95e7151b5f88831fb9906416e (patch)
tree831b7793cabc8dc01ad3cad05f7abf1b0ac99e6b /drivers/net/ixgbe/ixgbe_main.c
parent80605c6513207344d00b32e8d1e64bd34fdf1358 (diff)
ixgbe: consolidate MRQC and MTQC handling
The MRQC and MTQC registers are configured in the main setup path but are also reconfigured in the DCB setup path. The DCB path fixes the DCB configuration by configuring the SECTXMINIFG gap which is required for DCB pause to operate correctly. This patch reduces the duplicate code and does all setup in ixgbe_setup_mtqc() and ixgbe_setup_mrqc(). Additionally, this removes the IXGBE_QDE. This write never set the WRITE bit in the register so the write was not actually doing anything. Also this was to clear the register but, it is never set and defaults to zero. If this is needed for SRIOV it should be added correctly in a follow up patch. But it's never been working so removing it here should be OK. Signed-off-by: John Fastabend <john.r.fastabend@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ixgbe/ixgbe_main.c')
-rw-r--r--drivers/net/ixgbe/ixgbe_main.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c
index fba1e323495..20467da4f90 100644
--- a/drivers/net/ixgbe/ixgbe_main.c
+++ b/drivers/net/ixgbe/ixgbe_main.c
@@ -2816,6 +2816,7 @@ static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
struct ixgbe_hw *hw = &adapter->hw;
u32 rttdcs;
u32 mask;
+ u32 reg;
if (hw->mac.type == ixgbe_mac_82598EB)
return;
@@ -2838,6 +2839,12 @@ static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
/* We enable 8 traffic classes, DCB only */
IXGBE_WRITE_REG(hw, IXGBE_MTQC,
(IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
+
+ /* Enable Security TX Buffer IFG for DCB */
+ reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
+ reg |= IXGBE_SECTX_DCB;
+ IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
+
break;
default: