unicore32 additional architecture files: float point handling
This patch implements support for float point unit, which using UniCore-F64 FPU hardware in UniCore32 ISA. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Acked-by: Arnd Bergmann <arnd@arndb.de>
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GuanXuetao
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/*
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* linux/arch/unicore32/include/asm/fpstate.h
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*
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* Code specific to PKUnity SoC and UniCore ISA
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*
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* Copyright (C) 2001-2010 GUAN Xue-tao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __UNICORE_FPSTATE_H__
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#define __UNICORE_FPSTATE_H__
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#ifndef __ASSEMBLY__
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#define FP_REGS_NUMBER 33
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struct fp_state {
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unsigned int regs[FP_REGS_NUMBER];
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} __attribute__((aligned(8)));
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#endif
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#endif
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/*
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* linux/arch/unicore32/include/asm/fpu-ucf64.h
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*
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* Code specific to PKUnity SoC and UniCore ISA
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*
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* Maintained by GUAN Xue-tao <gxt@mprc.pku.edu.cn>
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* Copyright (C) 2001-2010 Guan Xuetao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#define FPSCR s31
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/* FPSCR bits */
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#define FPSCR_DEFAULT_NAN (1<<25)
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#define FPSCR_CMPINSTR_BIT (1<<31)
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#define FPSCR_CON (1<<29)
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#define FPSCR_TRAP (1<<27)
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/* RND mode */
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#define FPSCR_ROUND_NEAREST (0<<0)
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#define FPSCR_ROUND_PLUSINF (2<<0)
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#define FPSCR_ROUND_MINUSINF (3<<0)
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#define FPSCR_ROUND_TOZERO (1<<0)
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#define FPSCR_RMODE_BIT (0)
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#define FPSCR_RMODE_MASK (7 << FPSCR_RMODE_BIT)
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/* trap enable */
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#define FPSCR_IOE (1<<16)
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#define FPSCR_OFE (1<<14)
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#define FPSCR_UFE (1<<13)
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#define FPSCR_IXE (1<<12)
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#define FPSCR_HIE (1<<11)
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#define FPSCR_NDE (1<<10) /* non denomal */
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/* flags */
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#define FPSCR_IDC (1<<24)
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#define FPSCR_HIC (1<<23)
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#define FPSCR_IXC (1<<22)
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#define FPSCR_OFC (1<<21)
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#define FPSCR_UFC (1<<20)
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#define FPSCR_IOC (1<<19)
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/* stick bits */
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#define FPSCR_IOS (1<<9)
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#define FPSCR_OFS (1<<7)
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#define FPSCR_UFS (1<<6)
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#define FPSCR_IXS (1<<5)
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#define FPSCR_HIS (1<<4)
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#define FPSCR_NDS (1<<3) /*non denomal */
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/*
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* linux/arch/unicore32/kernel/fpu-ucf64.c
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*
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* Code specific to PKUnity SoC and UniCore ISA
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*
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* Copyright (C) 2001-2010 GUAN Xue-tao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <asm/fpu-ucf64.h>
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/*
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* A special flag to tell the normalisation code not to normalise.
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*/
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#define F64_NAN_FLAG 0x100
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/*
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* A bit pattern used to indicate the initial (unset) value of the
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* exception mask, in case nothing handles an instruction. This
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* doesn't include the NAN flag, which get masked out before
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* we check for an error.
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*/
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#define F64_EXCEPTION_ERROR ((u32)-1 & ~F64_NAN_FLAG)
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/*
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* Since we aren't building with -mfpu=f64, we need to code
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* these instructions using their MRC/MCR equivalents.
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*/
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#define f64reg(_f64_) #_f64_
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#define cff(_f64_) ({ \
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u32 __v; \
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asm("cff %0, " f64reg(_f64_) "@ fmrx %0, " #_f64_ \
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: "=r" (__v) : : "cc"); \
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__v; \
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})
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#define ctf(_f64_, _var_) \
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asm("ctf %0, " f64reg(_f64_) "@ fmxr " #_f64_ ", %0" \
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: : "r" (_var_) : "cc")
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/*
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* Raise a SIGFPE for the current process.
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* sicode describes the signal being raised.
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*/
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void ucf64_raise_sigfpe(unsigned int sicode, struct pt_regs *regs)
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{
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siginfo_t info;
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memset(&info, 0, sizeof(info));
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info.si_signo = SIGFPE;
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info.si_code = sicode;
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info.si_addr = (void __user *)(instruction_pointer(regs) - 4);
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/*
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* This is the same as NWFPE, because it's not clear what
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* this is used for
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*/
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current->thread.error_code = 0;
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current->thread.trap_no = 6;
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send_sig_info(SIGFPE, &info, current);
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}
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/*
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* Handle exceptions of UniCore-F64.
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*/
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void ucf64_exchandler(u32 inst, u32 fpexc, struct pt_regs *regs)
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{
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u32 tmp = fpexc;
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u32 exc = F64_EXCEPTION_ERROR & fpexc;
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pr_debug("UniCore-F64: instruction %08x fpscr %08x\n",
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inst, fpexc);
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if (exc & FPSCR_CMPINSTR_BIT) {
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if (exc & FPSCR_CON)
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tmp |= FPSCR_CON;
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else
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tmp &= ~(FPSCR_CON);
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exc &= ~(FPSCR_CMPINSTR_BIT | FPSCR_CON);
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} else {
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pr_debug(KERN_ERR "UniCore-F64 Error: unhandled exceptions\n");
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pr_debug(KERN_ERR "UniCore-F64 FPSCR 0x%08x INST 0x%08x\n",
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cff(FPSCR), inst);
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ucf64_raise_sigfpe(0, regs);
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return;
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}
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/*
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* Update the FPSCR with the additional exception flags.
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* Comparison instructions always return at least one of
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* these flags set.
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*/
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tmp &= ~(FPSCR_TRAP | FPSCR_IOS | FPSCR_OFS | FPSCR_UFS |
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FPSCR_IXS | FPSCR_HIS | FPSCR_IOC | FPSCR_OFC |
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FPSCR_UFC | FPSCR_IXC | FPSCR_HIC);
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tmp |= exc;
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ctf(FPSCR, tmp);
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}
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/*
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* F64 support code initialisation.
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*/
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static int __init ucf64_init(void)
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{
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ctf(FPSCR, 0x0); /* FPSCR_UFE | FPSCR_NDE perhaps better */
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printk(KERN_INFO "Enable UniCore-F64 support.\n");
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return 0;
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}
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late_initcall(ucf64_init);
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