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dma: fix comments

Correct spelling typo in drivers/dma.

Signed-off-by: Masanari Iida <standby24x7@gmail.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
This commit is contained in:
Masanari Iida 2012-08-04 23:37:53 +09:00 committed by Jiri Kosina
parent 886db6acf4
commit d73111c6d4
8 changed files with 14 additions and 14 deletions

View File

@ -169,9 +169,9 @@ static void atc_desc_put(struct at_dma_chan *atchan, struct at_desc *desc)
} }
/** /**
* atc_desc_chain - build chain adding a descripor * atc_desc_chain - build chain adding a descriptor
* @first: address of first descripor of the chain * @first: address of first descriptor of the chain
* @prev: address of previous descripor of the chain * @prev: address of previous descriptor of the chain
* @desc: descriptor to queue * @desc: descriptor to queue
* *
* Called from prep_* functions * Called from prep_* functions
@ -786,7 +786,7 @@ err_out:
} }
/** /**
* atc_dma_cyclic_fill_desc - Fill one period decriptor * atc_dma_cyclic_fill_desc - Fill one period descriptor
*/ */
static int static int
atc_dma_cyclic_fill_desc(struct dma_chan *chan, struct at_desc *desc, atc_dma_cyclic_fill_desc(struct dma_chan *chan, struct at_desc *desc,

View File

@ -1118,7 +1118,7 @@ fail:
* @chan: channel * @chan: channel
* @dma_addr: DMA mapped address of the buffer * @dma_addr: DMA mapped address of the buffer
* @buf_len: length of the buffer (in bytes) * @buf_len: length of the buffer (in bytes)
* @period_len: lenght of a single period * @period_len: length of a single period
* @dir: direction of the operation * @dir: direction of the operation
* @context: operation context (ignored) * @context: operation context (ignored)
* *

View File

@ -1015,7 +1015,7 @@ static irqreturn_t fsldma_chan_irq(int irq, void *data)
/* /*
* Programming Error * Programming Error
* The DMA_INTERRUPT async_tx is a NULL transfer, which will * The DMA_INTERRUPT async_tx is a NULL transfer, which will
* triger a PE interrupt. * trigger a PE interrupt.
*/ */
if (stat & FSL_DMA_SR_PE) { if (stat & FSL_DMA_SR_PE) {
chan_dbg(chan, "irq: Programming Error INT\n"); chan_dbg(chan, "irq: Programming Error INT\n");

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@ -571,8 +571,8 @@ static void imxdma_tasklet(unsigned long data)
if (desc->desc.callback) if (desc->desc.callback)
desc->desc.callback(desc->desc.callback_param); desc->desc.callback(desc->desc.callback_param);
/* If we are dealing with a cyclic descriptor keep it on ld_active /* If we are dealing with a cyclic descriptor, keep it on ld_active
* and dont mark the descripor as complete. * and dont mark the descriptor as complete.
* Only in non-cyclic cases it would be marked as complete * Only in non-cyclic cases it would be marked as complete
*/ */
if (imxdma_chan_is_doing_cyclic(imxdmac)) if (imxdma_chan_is_doing_cyclic(imxdmac))

View File

@ -168,9 +168,9 @@ union intel_mid_dma_cfg_hi {
* @active_list: current active descriptors * @active_list: current active descriptors
* @queue: current queued up descriptors * @queue: current queued up descriptors
* @free_list: current free descriptors * @free_list: current free descriptors
* @slave: dma slave struture * @slave: dma slave structure
* @descs_allocated: total number of decsiptors allocated * @descs_allocated: total number of descriptors allocated
* @dma: dma device struture pointer * @dma: dma device structure pointer
* @busy: bool representing if ch is busy (active txn) or not * @busy: bool representing if ch is busy (active txn) or not
* @in_use: bool representing if ch is in use or not * @in_use: bool representing if ch is in use or not
* @raw_tfr: raw trf interrupt received * @raw_tfr: raw trf interrupt received

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@ -522,7 +522,7 @@ enum desc_status {
/* In the DMAC pool */ /* In the DMAC pool */
FREE, FREE,
/* /*
* Allocted to some channel during prep_xxx * Allocated to some channel during prep_xxx
* Also may be sitting on the work_list. * Also may be sitting on the work_list.
*/ */
PREP, PREP,

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@ -4446,7 +4446,7 @@ static int __devinit ppc440spe_adma_probe(struct platform_device *ofdev)
ret = -ENOMEM; ret = -ENOMEM;
goto err_dma_alloc; goto err_dma_alloc;
} }
dev_dbg(&ofdev->dev, "allocted descriptor pool virt 0x%p phys 0x%llx\n", dev_dbg(&ofdev->dev, "allocated descriptor pool virt 0x%p phys 0x%llx\n",
adev->dma_desc_pool_virt, (u64)adev->dma_desc_pool); adev->dma_desc_pool_virt, (u64)adev->dma_desc_pool);
regs = ioremap(res.start, resource_size(&res)); regs = ioremap(res.start, resource_size(&res));

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@ -202,7 +202,7 @@
/* LLI related structures */ /* LLI related structures */
/** /**
* struct d40_phy_lli - The basic configration register for each physical * struct d40_phy_lli - The basic configuration register for each physical
* channel. * channel.
* *
* @reg_cfg: The configuration register. * @reg_cfg: The configuration register.