sh: Add initial support for SH7757 CPU subtype
Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Yoshihiro Shimoda
Paul Mundt
parent
9e7291c112
commit
c01f0f1a4a
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@ -396,6 +396,13 @@ config CPU_SUBTYPE_SH7724
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help
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Select SH7724 if you have an SH-MobileR2R CPU.
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config CPU_SUBTYPE_SH7757
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bool "Support SH7757 processor"
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select CPU_SH4A
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select CPU_SHX2
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help
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Select SH7757 if you have a SH4A SH7757 CPU.
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config CPU_SUBTYPE_SH7763
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bool "Support SH7763 processor"
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select CPU_SH4A
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@ -38,6 +38,7 @@ config EARLY_SCIF_CONSOLE_PORT
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default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763 || \
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CPU_SUBTYPE_SH7722 || CPU_SUBTYPE_SH7366 || \
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CPU_SUBTYPE_SH7343
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default "0xfe4c0000" if CPU_SUBTYPE_SH7757
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default "0xffeb0000" if CPU_SUBTYPE_SH7785
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default "0xffeb0000" if CPU_SUBTYPE_SH7786
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default "0xfffe8000" if CPU_SUBTYPE_SH7203
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@ -32,7 +32,7 @@ enum cpu_type {
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/* SH-4A types */
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CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
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CPU_SH7723, CPU_SH7724, CPU_SHX3,
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CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SHX3,
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/* SH4AL-DSP types */
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CPU_SH7343, CPU_SH7722, CPU_SH7366,
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@ -22,6 +22,10 @@
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#define MSTPCR0 0xa4150030
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#define MSTPCR1 0xa4150034
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#define MSTPCR2 0xa4150038
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#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
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#define FRQCR 0xffc80000
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#define OSCCR 0xffc80018
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#define PLLCR 0xffc80024
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#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
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defined(CONFIG_CPU_SUBTYPE_SH7780)
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#define FRQCR 0xffc80000
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@ -0,0 +1,243 @@
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#ifndef __ASM_SH7757_H__
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#define __ASM_SH7757_H__
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enum {
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/* PTA */
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GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4,
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GPIO_PTA3, GPIO_PTA2, GPIO_PTA1, GPIO_PTA0,
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/* PTB */
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GPIO_PTB7, GPIO_PTB6, GPIO_PTB5, GPIO_PTB4,
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GPIO_PTB3, GPIO_PTB2, GPIO_PTB1, GPIO_PTB0,
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/* PTC */
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GPIO_PTC7, GPIO_PTC6, GPIO_PTC5, GPIO_PTC4,
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GPIO_PTC3, GPIO_PTC2, GPIO_PTC1, GPIO_PTC0,
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/* PTD */
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GPIO_PTD7, GPIO_PTD6, GPIO_PTD5, GPIO_PTD4,
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GPIO_PTD3, GPIO_PTD2, GPIO_PTD1, GPIO_PTD0,
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/* PTE */
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GPIO_PTE7, GPIO_PTE6, GPIO_PTE5, GPIO_PTE4,
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GPIO_PTE3, GPIO_PTE2, GPIO_PTE1, GPIO_PTE0,
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/* PTF */
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GPIO_PTF7, GPIO_PTF6, GPIO_PTF5, GPIO_PTF4,
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GPIO_PTF3, GPIO_PTF2, GPIO_PTF1, GPIO_PTF0,
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/* PTG */
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GPIO_PTG7, GPIO_PTG6, GPIO_PTG5, GPIO_PTG4,
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GPIO_PTG3, GPIO_PTG2, GPIO_PTG1, GPIO_PTG0,
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/* PTH */
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GPIO_PTH7, GPIO_PTH6, GPIO_PTH5, GPIO_PTH4,
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GPIO_PTH3, GPIO_PTH2, GPIO_PTH1, GPIO_PTH0,
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/* PTI */
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GPIO_PTI7, GPIO_PTI6, GPIO_PTI5, GPIO_PTI4,
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GPIO_PTI3, GPIO_PTI2, GPIO_PTI1, GPIO_PTI0,
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/* PTJ */
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GPIO_PTJ7, GPIO_PTJ6, GPIO_PTJ5, GPIO_PTJ4,
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GPIO_PTJ3, GPIO_PTJ2, GPIO_PTJ1, GPIO_PTJ0,
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/* PTK */
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GPIO_PTK7, GPIO_PTK6, GPIO_PTK5, GPIO_PTK4,
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GPIO_PTK3, GPIO_PTK2, GPIO_PTK1, GPIO_PTK0,
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/* PTL */
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GPIO_PTL7, GPIO_PTL6, GPIO_PTL5, GPIO_PTL4,
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GPIO_PTL3, GPIO_PTL2, GPIO_PTL1, GPIO_PTL0,
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/* PTM */
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GPIO_PTM6, GPIO_PTM5, GPIO_PTM4,
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GPIO_PTM3, GPIO_PTM2, GPIO_PTM1, GPIO_PTM0,
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/* PTN */
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GPIO_PTN7, GPIO_PTN6, GPIO_PTN5, GPIO_PTN4,
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GPIO_PTN3, GPIO_PTN2, GPIO_PTN1, GPIO_PTN0,
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/* PTO */
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GPIO_PTO7, GPIO_PTO6, GPIO_PTO5, GPIO_PTO4,
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GPIO_PTO3, GPIO_PTO2, GPIO_PTO1, GPIO_PTO0,
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/* PTP */
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GPIO_PTP6, GPIO_PTP5, GPIO_PTP4,
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GPIO_PTP3, GPIO_PTP2, GPIO_PTP1, GPIO_PTP0,
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/* PTQ */
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GPIO_PTQ6, GPIO_PTQ5, GPIO_PTQ4,
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GPIO_PTQ3, GPIO_PTQ2, GPIO_PTQ1, GPIO_PTQ0,
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/* PTR */
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GPIO_PTR7, GPIO_PTR6, GPIO_PTR5, GPIO_PTR4,
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GPIO_PTR3, GPIO_PTR2, GPIO_PTR1, GPIO_PTR0,
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/* PTS */
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GPIO_PTS7, GPIO_PTS6, GPIO_PTS5, GPIO_PTS4,
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GPIO_PTS3, GPIO_PTS2, GPIO_PTS1, GPIO_PTS0,
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/* PTT */
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GPIO_PTT5, GPIO_PTT4,
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GPIO_PTT3, GPIO_PTT2, GPIO_PTT1, GPIO_PTT0,
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/* PTU */
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GPIO_PTU7, GPIO_PTU6, GPIO_PTU5, GPIO_PTU4,
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GPIO_PTU3, GPIO_PTU2, GPIO_PTU1, GPIO_PTU0,
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/* PTV */
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GPIO_PTV7, GPIO_PTV6, GPIO_PTV5, GPIO_PTV4,
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GPIO_PTV3, GPIO_PTV2, GPIO_PTV1, GPIO_PTV0,
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/* PTW */
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GPIO_PTW7, GPIO_PTW6, GPIO_PTW5, GPIO_PTW4,
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GPIO_PTW3, GPIO_PTW2, GPIO_PTW1, GPIO_PTW0,
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/* PTX */
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GPIO_PTX7, GPIO_PTX6, GPIO_PTX5, GPIO_PTX4,
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GPIO_PTX3, GPIO_PTX2, GPIO_PTX1, GPIO_PTX0,
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/* PTY */
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GPIO_PTY7, GPIO_PTY6, GPIO_PTY5, GPIO_PTY4,
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GPIO_PTY3, GPIO_PTY2, GPIO_PTY1, GPIO_PTY0,
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/* PTZ */
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GPIO_PTZ7, GPIO_PTZ6, GPIO_PTZ5, GPIO_PTZ4,
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GPIO_PTZ3, GPIO_PTZ2, GPIO_PTZ1, GPIO_PTZ0,
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/* PTA (mobule: LBSC, CPG, LPC) */
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GPIO_FN_BS, GPIO_FN_RDWR, GPIO_FN_WE1, GPIO_FN_RDY,
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GPIO_FN_MD10, GPIO_FN_MD9, GPIO_FN_MD8,
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GPIO_FN_LGPIO7, GPIO_FN_LGPIO6, GPIO_FN_LGPIO5, GPIO_FN_LGPIO4,
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GPIO_FN_LGPIO3, GPIO_FN_LGPIO2, GPIO_FN_LGPIO1, GPIO_FN_LGPIO0,
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/* PTB (mobule: LBSC, EtherC, SIM, LPC) */
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GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12,
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GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8,
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GPIO_FN_ET0_MDC, GPIO_FN_ET0_MDIO,
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GPIO_FN_ET1_MDC, GPIO_FN_ET1_MDIO,
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GPIO_FN_SIM_D, GPIO_FN_SIM_CLK, GPIO_FN_SIM_RST,
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GPIO_FN_WPSZ1, GPIO_FN_WPSZ0, GPIO_FN_FWID, GPIO_FN_FLSHSZ,
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GPIO_FN_LPC_SPIEN, GPIO_FN_BASEL,
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/* PTC (mobule: SD) */
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GPIO_FN_SD_WP, GPIO_FN_SD_CD, GPIO_FN_SD_CLK, GPIO_FN_SD_CMD,
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GPIO_FN_SD_D3, GPIO_FN_SD_D2, GPIO_FN_SD_D1, GPIO_FN_SD_D0,
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/* PTD (mobule: INTC, SPI0, LBSC, CPG, ADC) */
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GPIO_FN_IRQ7, GPIO_FN_IRQ6, GPIO_FN_IRQ5, GPIO_FN_IRQ4,
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GPIO_FN_IRQ3, GPIO_FN_IRQ2, GPIO_FN_IRQ1, GPIO_FN_IRQ0,
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GPIO_FN_MD6, GPIO_FN_MD5, GPIO_FN_MD3, GPIO_FN_MD2,
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GPIO_FN_MD1, GPIO_FN_MD0, GPIO_FN_ADTRG1, GPIO_FN_ADTRG0,
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/* PTE (mobule: EtherC) */
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GPIO_FN_ET0_CRS_DV, GPIO_FN_ET0_TXD1,
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GPIO_FN_ET0_TXD0, GPIO_FN_ET0_TX_EN,
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GPIO_FN_ET0_REF_CLK, GPIO_FN_ET0_RXD1,
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GPIO_FN_ET0_RXD0, GPIO_FN_ET0_RX_ER,
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/* PTF (mobule: EtherC) */
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GPIO_FN_ET1_CRS_DV, GPIO_FN_ET1_TXD1,
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GPIO_FN_ET1_TXD0, GPIO_FN_ET1_TX_EN,
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GPIO_FN_ET1_REF_CLK, GPIO_FN_ET1_RXD1,
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GPIO_FN_ET1_RXD0, GPIO_FN_ET1_RX_ER,
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/* PTG (mobule: SYSTEM, PWMX, LPC) */
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GPIO_FN_STATUS0, GPIO_FN_STATUS1,
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GPIO_FN_PWX0, GPIO_FN_PWX1, GPIO_FN_PWX2, GPIO_FN_PWX3,
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GPIO_FN_SERIRQ, GPIO_FN_CLKRUN, GPIO_FN_LPCPD, GPIO_FN_LDRQ,
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/* PTH (mobule: TMU, SCIF234, SPI1, SPI0) */
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GPIO_FN_TCLK, GPIO_FN_RXD4, GPIO_FN_TXD4,
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GPIO_FN_SP1_MOSI, GPIO_FN_SP1_MISO,
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GPIO_FN_SP1_SCK, GPIO_FN_SP1_SCK_FB,
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GPIO_FN_SP1_SS0, GPIO_FN_SP1_SS1,
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GPIO_FN_SP0_SS1,
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/* PTI (mobule: INTC) */
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GPIO_FN_IRQ15, GPIO_FN_IRQ14, GPIO_FN_IRQ13, GPIO_FN_IRQ12,
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GPIO_FN_IRQ11, GPIO_FN_IRQ10, GPIO_FN_IRQ9, GPIO_FN_IRQ8,
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/* PTJ (mobule: SCIF234, SERMUX) */
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GPIO_FN_RXD3, GPIO_FN_TXD3, GPIO_FN_RXD2, GPIO_FN_TXD2,
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GPIO_FN_COM1_TXD, GPIO_FN_COM1_RXD,
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GPIO_FN_COM1_RTS, GPIO_FN_COM1_CTS,
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/* PTK (mobule: SERMUX) */
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GPIO_FN_COM2_TXD, GPIO_FN_COM2_RXD,
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GPIO_FN_COM2_RTS, GPIO_FN_COM2_CTS,
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GPIO_FN_COM2_DTR, GPIO_FN_COM2_DSR,
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GPIO_FN_COM2_DCD, GPIO_FN_COM2_RI,
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/* PTL (mobule: SERMUX) */
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GPIO_FN_RAC_TXD, GPIO_FN_RAC_RXD,
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GPIO_FN_RAC_RTS, GPIO_FN_RAC_CTS,
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GPIO_FN_RAC_DTR, GPIO_FN_RAC_DSR,
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GPIO_FN_RAC_DCD, GPIO_FN_RAC_RI,
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/* PTM (mobule: IIC, LPC) */
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GPIO_FN_SDA6, GPIO_FN_SCL6, GPIO_FN_SDA7, GPIO_FN_SCL7,
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GPIO_FN_WP, GPIO_FN_FMS0, GPIO_FN_FMS1,
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/* PTN (mobule: SCIF234, EVC) */
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GPIO_FN_SCK2, GPIO_FN_RTS4, GPIO_FN_RTS3, GPIO_FN_RTS2,
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GPIO_FN_CTS4, GPIO_FN_CTS3, GPIO_FN_CTS2,
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GPIO_FN_EVENT7, GPIO_FN_EVENT6, GPIO_FN_EVENT5, GPIO_FN_EVENT4,
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GPIO_FN_EVENT3, GPIO_FN_EVENT2, GPIO_FN_EVENT1, GPIO_FN_EVENT0,
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/* PTO (mobule: SGPIO) */
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GPIO_FN_SGPIO0_CLK, GPIO_FN_SGPIO0_LOAD,
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GPIO_FN_SGPIO0_DI, GPIO_FN_SGPIO0_DO,
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GPIO_FN_SGPIO1_CLK, GPIO_FN_SGPIO1_LOAD,
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GPIO_FN_SGPIO1_DI, GPIO_FN_SGPIO1_DO,
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/* PTP (mobule: JMC, SCIF234) */
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GPIO_FN_JMCTCK, GPIO_FN_JMCTMS, GPIO_FN_JMCTDO, GPIO_FN_JMCTDI,
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GPIO_FN_JMCRST, GPIO_FN_SCK4, GPIO_FN_SCK3,
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/* PTQ (mobule: LPC) */
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GPIO_FN_LAD3, GPIO_FN_LAD2, GPIO_FN_LAD1, GPIO_FN_LAD0,
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GPIO_FN_LFRAME, GPIO_FN_LRESET, GPIO_FN_LCLK,
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/* PTR (mobule: GRA, IIC) */
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GPIO_FN_DDC3, GPIO_FN_DDC2,
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GPIO_FN_SDA8, GPIO_FN_SCL8, GPIO_FN_SDA2, GPIO_FN_SCL2,
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GPIO_FN_SDA1, GPIO_FN_SCL1, GPIO_FN_SDA0, GPIO_FN_SCL0,
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/* PTS (mobule: GRA, IIC) */
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GPIO_FN_DDC1, GPIO_FN_DDC0,
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GPIO_FN_SDA9, GPIO_FN_SCL9, GPIO_FN_SDA5, GPIO_FN_SCL5,
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GPIO_FN_SDA4, GPIO_FN_SCL4, GPIO_FN_SDA3, GPIO_FN_SCL3,
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/* PTT (mobule: SYSTEM, PWMX) */
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GPIO_FN_AUDSYNC, GPIO_FN_AUDCK,
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GPIO_FN_AUDATA3, GPIO_FN_AUDATA2,
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GPIO_FN_AUDATA1, GPIO_FN_AUDATA0,
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GPIO_FN_PWX7, GPIO_FN_PWX6, GPIO_FN_PWX5, GPIO_FN_PWX4,
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/* PTU (mobule: LBSC, DMAC) */
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GPIO_FN_CS6, GPIO_FN_CS5, GPIO_FN_CS4, GPIO_FN_CS0,
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GPIO_FN_RD, GPIO_FN_WE0, GPIO_FN_A25, GPIO_FN_A24,
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GPIO_FN_DREQ0, GPIO_FN_DACK0,
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/* PTV (mobule: LBSC, DMAC) */
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GPIO_FN_A23, GPIO_FN_A22, GPIO_FN_A21, GPIO_FN_A20,
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GPIO_FN_A19, GPIO_FN_A18, GPIO_FN_A17, GPIO_FN_A16,
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GPIO_FN_TEND0, GPIO_FN_DREQ1, GPIO_FN_DACK1, GPIO_FN_TEND1,
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/* PTW (mobule: LBSC) */
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GPIO_FN_A15, GPIO_FN_A14, GPIO_FN_A13, GPIO_FN_A12,
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GPIO_FN_A11, GPIO_FN_A10, GPIO_FN_A9, GPIO_FN_A8,
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/* PTX (mobule: LBSC) */
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GPIO_FN_A7, GPIO_FN_A6, GPIO_FN_A5, GPIO_FN_A4,
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GPIO_FN_A3, GPIO_FN_A2, GPIO_FN_A1, GPIO_FN_A0,
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/* PTY (mobule: LBSC) */
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GPIO_FN_D7, GPIO_FN_D6, GPIO_FN_D5, GPIO_FN_D4,
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GPIO_FN_D3, GPIO_FN_D2, GPIO_FN_D1, GPIO_FN_D0,
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};
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#endif /* __ASM_SH7757_H__ */
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@ -139,8 +139,15 @@ int __init detect_cpu_and_cache_system(void)
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}
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break;
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case 0x300b:
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boot_cpu_data.type = CPU_SH7724;
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boot_cpu_data.flags |= CPU_HAS_L2_CACHE;
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switch (prr) {
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case 0x20:
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boot_cpu_data.type = CPU_SH7723;
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boot_cpu_data.flags |= CPU_HAS_L2_CACHE;
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break;
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case 0x50:
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boot_cpu_data.type = CPU_SH7757;
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break;
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}
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break;
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case 0x4000: /* 1st cut */
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case 0x4001: /* 2nd cut */
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@ -3,6 +3,7 @@
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#
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# CPU subtype setup
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obj-$(CONFIG_CPU_SUBTYPE_SH7757) += setup-sh7757.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7763) += setup-sh7763.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o
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@ -19,6 +20,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o
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smp-$(CONFIG_CPU_SHX3) := smp-shx3.o
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# Primary on-chip clocks (common)
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clock-$(CONFIG_CPU_SUBTYPE_SH7757) := clock-sh7757.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7763) := clock-sh7763.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o
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@ -35,6 +37,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
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pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o
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pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o
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pinmux-$(CONFIG_CPU_SUBTYPE_SH7724) := pinmux-sh7724.o
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pinmux-$(CONFIG_CPU_SUBTYPE_SH7757) := pinmux-sh7757.o
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pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o
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pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o
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@ -0,0 +1,130 @@
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/*
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* arch/sh/kernel/cpu/sh4/clock-sh7757.c
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*
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* SH7757 support for the clock framework
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*
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* Copyright (C) 2009 Renesas Solutions Corp.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <asm/clock.h>
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#include <asm/freq.h>
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||||
|
||||
static int ifc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
|
||||
16, 1, 1, 32, 1, 1, 1, 1 };
|
||||
static int sfc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
|
||||
16, 1, 1, 32, 1, 1, 1, 1 };
|
||||
static int bfc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
|
||||
16, 1, 1, 32, 1, 1, 1, 1 };
|
||||
static int p1fc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
|
||||
16, 1, 1, 32, 1, 1, 1, 1 };
|
||||
|
||||
static void master_clk_init(struct clk *clk)
|
||||
{
|
||||
clk->rate = CONFIG_SH_PCLK_FREQ * 16;
|
||||
}
|
||||
|
||||
static struct clk_ops sh7757_master_clk_ops = {
|
||||
.init = master_clk_init,
|
||||
};
|
||||
|
||||
static void module_clk_recalc(struct clk *clk)
|
||||
{
|
||||
int idx = ctrl_inl(FRQCR) & 0x0000000f;
|
||||
clk->rate = clk->parent->rate / p1fc_divisors[idx];
|
||||
}
|
||||
|
||||
static struct clk_ops sh7757_module_clk_ops = {
|
||||
.recalc = module_clk_recalc,
|
||||
};
|
||||
|
||||
static void bus_clk_recalc(struct clk *clk)
|
||||
{
|
||||
int idx = (ctrl_inl(FRQCR) >> 8) & 0x0000000f;
|
||||
clk->rate = clk->parent->rate / bfc_divisors[idx];
|
||||
}
|
||||
|
||||
static struct clk_ops sh7757_bus_clk_ops = {
|
||||
.recalc = bus_clk_recalc,
|
||||
};
|
||||
|
||||
static void cpu_clk_recalc(struct clk *clk)
|
||||
{
|
||||
int idx = (ctrl_inl(FRQCR) >> 20) & 0x0000000f;
|
||||
clk->rate = clk->parent->rate / ifc_divisors[idx];
|
||||
}
|
||||
|
||||
static struct clk_ops sh7757_cpu_clk_ops = {
|
||||
.recalc = cpu_clk_recalc,
|
||||
};
|
||||
|
||||
static struct clk_ops *sh7757_clk_ops[] = {
|
||||
&sh7757_master_clk_ops,
|
||||
&sh7757_module_clk_ops,
|
||||
&sh7757_bus_clk_ops,
|
||||
&sh7757_cpu_clk_ops,
|
||||
};
|
||||
|
||||
void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
|
||||
{
|
||||
if (idx < ARRAY_SIZE(sh7757_clk_ops))
|
||||
*ops = sh7757_clk_ops[idx];
|
||||
}
|
||||
|
||||
static void shyway_clk_recalc(struct clk *clk)
|
||||
{
|
||||
int idx = (ctrl_inl(FRQCR) >> 12) & 0x0000000f;
|
||||
clk->rate = clk->parent->rate / sfc_divisors[idx];
|
||||
}
|
||||
|
||||
static struct clk_ops sh7757_shyway_clk_ops = {
|
||||
.recalc = shyway_clk_recalc,
|
||||
};
|
||||
|
||||
static struct clk sh7757_shyway_clk = {
|
||||
.name = "shyway_clk",
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
.ops = &sh7757_shyway_clk_ops,
|
||||
};
|
||||
|
||||
/*
|
||||
* Additional sh7757-specific on-chip clocks that aren't already part of the
|
||||
* clock framework
|
||||
*/
|
||||
static struct clk *sh7757_onchip_clocks[] = {
|
||||
&sh7757_shyway_clk,
|
||||
};
|
||||
|
||||
static int __init sh7757_clk_init(void)
|
||||
{
|
||||
struct clk *clk = clk_get(NULL, "master_clk");
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(sh7757_onchip_clocks); i++) {
|
||||
struct clk *clkp = sh7757_onchip_clocks[i];
|
||||
|
||||
clkp->parent = clk;
|
||||
clk_register(clkp);
|
||||
clk_enable(clkp);
|
||||
}
|
||||
|
||||
/*
|
||||
* Now that we have the rest of the clocks registered, we need to
|
||||
* force the parent clock to propagate so that these clocks will
|
||||
* automatically figure out their rate. We cheat by handing the
|
||||
* parent clock its current rate and forcing child propagation.
|
||||
*/
|
||||
clk_set_rate(clk, clk_get_rate(clk));
|
||||
|
||||
clk_put(clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(sh7757_clk_init);
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,513 @@
|
|||
/*
|
||||
* SH7757 Setup
|
||||
*
|
||||
* Copyright (C) 2009 Renesas Solutions Corp.
|
||||
*
|
||||
* based on setup-sh7785.c : Copyright (C) 2007 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/serial.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/sh_timer.h>
|
||||
|
||||
static struct sh_timer_config tmu0_platform_data = {
|
||||
.name = "TMU0",
|
||||
.channel_offset = 0x04,
|
||||
.timer_bit = 0,
|
||||
.clk = "peripheral_clk",
|
||||
.clockevent_rating = 200,
|
||||
};
|
||||
|
||||
static struct resource tmu0_resources[] = {
|
||||
[0] = {
|
||||
.name = "TMU0",
|
||||
.start = 0xfe430008,
|
||||
.end = 0xfe430013,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 28,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device tmu0_device = {
|
||||
.name = "sh_tmu",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &tmu0_platform_data,
|
||||
},
|
||||
.resource = tmu0_resources,
|
||||
.num_resources = ARRAY_SIZE(tmu0_resources),
|
||||
};
|
||||
|
||||
static struct sh_timer_config tmu1_platform_data = {
|
||||
.name = "TMU1",
|
||||
.channel_offset = 0x10,
|
||||
.timer_bit = 1,
|
||||
.clk = "peripheral_clk",
|
||||
.clocksource_rating = 200,
|
||||
};
|
||||
|
||||
static struct resource tmu1_resources[] = {
|
||||
[0] = {
|
||||
.name = "TMU1",
|
||||
.start = 0xfe430014,
|
||||
.end = 0xfe43001f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 29,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device tmu1_device = {
|
||||
.name = "sh_tmu",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.platform_data = &tmu1_platform_data,
|
||||
},
|
||||
.resource = tmu1_resources,
|
||||
.num_resources = ARRAY_SIZE(tmu1_resources),
|
||||
};
|
||||
|
||||
static struct plat_sci_port sci_platform_data[] = {
|
||||
{
|
||||
.mapbase = 0xfe4b0000, /* SCIF2 */
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 40, 40, 40, 40 },
|
||||
}, {
|
||||
.mapbase = 0xfe4c0000, /* SCIF3 */
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 76, 76, 76, 76 },
|
||||
}, {
|
||||
.mapbase = 0xfe4d0000, /* SCIF4 */
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 104, 104, 104, 104 },
|
||||
}, {
|
||||
.flags = 0,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device sci_device = {
|
||||
.name = "sh-sci",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = sci_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *sh7757_devices[] __initdata = {
|
||||
&tmu0_device,
|
||||
&tmu1_device,
|
||||
&sci_device,
|
||||
};
|
||||
|
||||
static int __init sh7757_devices_setup(void)
|
||||
{
|
||||
return platform_add_devices(sh7757_devices,
|
||||
ARRAY_SIZE(sh7757_devices));
|
||||
}
|
||||
arch_initcall(sh7757_devices_setup);
|
||||
|
||||
enum {
|
||||
UNUSED = 0,
|
||||
|
||||
/* interrupt sources */
|
||||
|
||||
IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
|
||||
IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
|
||||
IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
|
||||
IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
|
||||
|
||||
IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
|
||||
IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
|
||||
IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
|
||||
IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
|
||||
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
|
||||
|
||||
SDHI,
|
||||
DVC,
|
||||
IRQ8, IRQ9, IRQ10,
|
||||
WDT0,
|
||||
TMU0, TMU1, TMU2, TMU2_TICPI,
|
||||
HUDI,
|
||||
|
||||
ARC4,
|
||||
DMAC0,
|
||||
IRQ11,
|
||||
SCIF2,
|
||||
DMAC1_6,
|
||||
USB0,
|
||||
IRQ12,
|
||||
JMC,
|
||||
SPI1,
|
||||
IRQ13, IRQ14,
|
||||
USB1,
|
||||
TMR01, TMR23, TMR45,
|
||||
WDT1,
|
||||
FRT,
|
||||
LPC,
|
||||
SCIF0, SCIF1, SCIF3,
|
||||
PECI0I, PECI1I, PECI2I,
|
||||
IRQ15,
|
||||
ETHERC,
|
||||
SPI0,
|
||||
ADC1,
|
||||
DMAC1_8,
|
||||
SIM,
|
||||
TMU3, TMU4, TMU5,
|
||||
ADC0,
|
||||
SCIF4,
|
||||
IIC0_0, IIC0_1, IIC0_2, IIC0_3,
|
||||
IIC1_0, IIC1_1, IIC1_2, IIC1_3,
|
||||
IIC2_0, IIC2_1, IIC2_2, IIC2_3,
|
||||
IIC3_0, IIC3_1, IIC3_2, IIC3_3,
|
||||
IIC4_0, IIC4_1, IIC4_2, IIC4_3,
|
||||
IIC5_0, IIC5_1, IIC5_2, IIC5_3,
|
||||
IIC6_0, IIC6_1, IIC6_2, IIC6_3,
|
||||
IIC7_0, IIC7_1, IIC7_2, IIC7_3,
|
||||
IIC8_0, IIC8_1, IIC8_2, IIC8_3,
|
||||
IIC9_0, IIC9_1, IIC9_2, IIC9_3,
|
||||
PCIINTA,
|
||||
PCIE,
|
||||
SGPIO,
|
||||
|
||||
/* interrupt groups */
|
||||
|
||||
TMU012, TMU345,
|
||||
};
|
||||
|
||||
static struct intc_vect vectors[] __initdata = {
|
||||
INTC_VECT(SDHI, 0x480), INTC_VECT(SDHI, 0x04a0),
|
||||
INTC_VECT(SDHI, 0x4c0),
|
||||
INTC_VECT(DVC, 0x4e0),
|
||||
INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520),
|
||||
INTC_VECT(IRQ10, 0x540),
|
||||
INTC_VECT(WDT0, 0x560),
|
||||
INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
|
||||
INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
|
||||
INTC_VECT(HUDI, 0x600),
|
||||
INTC_VECT(ARC4, 0x620),
|
||||
INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660),
|
||||
INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0),
|
||||
INTC_VECT(DMAC0, 0x6c0),
|
||||
INTC_VECT(IRQ11, 0x6e0),
|
||||
INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720),
|
||||
INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760),
|
||||
INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0),
|
||||
INTC_VECT(DMAC1_6, 0x7c0), INTC_VECT(DMAC1_6, 0x7e0),
|
||||
INTC_VECT(USB0, 0x840),
|
||||
INTC_VECT(IRQ12, 0x880),
|
||||
INTC_VECT(JMC, 0x8a0),
|
||||
INTC_VECT(SPI1, 0x8c0),
|
||||
INTC_VECT(IRQ13, 0x8e0), INTC_VECT(IRQ14, 0x900),
|
||||
INTC_VECT(USB1, 0x920),
|
||||
INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20),
|
||||
INTC_VECT(TMR45, 0xa40),
|
||||
INTC_VECT(WDT1, 0xa60),
|
||||
INTC_VECT(FRT, 0xa80),
|
||||
INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0),
|
||||
INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00),
|
||||
INTC_VECT(LPC, 0xb20),
|
||||
INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60),
|
||||
INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0),
|
||||
INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0),
|
||||
INTC_VECT(PECI0I, 0xc00), INTC_VECT(PECI1I, 0xc20),
|
||||
INTC_VECT(PECI2I, 0xc40),
|
||||
INTC_VECT(IRQ15, 0xc60),
|
||||
INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0),
|
||||
INTC_VECT(SPI0, 0xcc0),
|
||||
INTC_VECT(ADC1, 0xce0),
|
||||
INTC_VECT(DMAC1_8, 0xd00), INTC_VECT(DMAC1_8, 0xd20),
|
||||
INTC_VECT(DMAC1_8, 0xd40), INTC_VECT(DMAC1_8, 0xd60),
|
||||
INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
|
||||
INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
|
||||
INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
|
||||
INTC_VECT(TMU5, 0xe40),
|
||||
INTC_VECT(ADC0, 0xe60),
|
||||
INTC_VECT(SCIF4, 0xf00), INTC_VECT(SCIF4, 0xf20),
|
||||
INTC_VECT(SCIF4, 0xf40), INTC_VECT(SCIF4, 0xf60),
|
||||
INTC_VECT(IIC0_0, 0x1400), INTC_VECT(IIC0_1, 0x1420),
|
||||
INTC_VECT(IIC0_2, 0x1440), INTC_VECT(IIC0_3, 0x1460),
|
||||
INTC_VECT(IIC1_0, 0x1480), INTC_VECT(IIC1_1, 0x14e0),
|
||||
INTC_VECT(IIC1_2, 0x1500), INTC_VECT(IIC1_3, 0x1520),
|
||||
INTC_VECT(IIC2_0, 0x1540), INTC_VECT(IIC2_1, 0x1560),
|
||||
INTC_VECT(IIC2_2, 0x1580), INTC_VECT(IIC2_3, 0x1600),
|
||||
INTC_VECT(IIC3_0, 0x1620), INTC_VECT(IIC3_1, 0x1640),
|
||||
INTC_VECT(IIC3_2, 0x16e0), INTC_VECT(IIC3_3, 0x1700),
|
||||
INTC_VECT(IIC4_0, 0x17c0), INTC_VECT(IIC4_1, 0x1800),
|
||||
INTC_VECT(IIC4_2, 0x1820), INTC_VECT(IIC4_3, 0x1840),
|
||||
INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880),
|
||||
INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0),
|
||||
INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900),
|
||||
INTC_VECT(IIC6_2, 0x1920), INTC_VECT(IIC6_3, 0x1980),
|
||||
INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00),
|
||||
INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40),
|
||||
INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80),
|
||||
INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40),
|
||||
INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80),
|
||||
INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20),
|
||||
INTC_VECT(PCIINTA, 0x1ce0),
|
||||
INTC_VECT(PCIE, 0x1e00),
|
||||
INTC_VECT(SGPIO, 0x1f80),
|
||||
INTC_VECT(SGPIO, 0x1fa0),
|
||||
};
|
||||
|
||||
static struct intc_group groups[] __initdata = {
|
||||
INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
|
||||
INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
|
||||
};
|
||||
|
||||
static struct intc_mask_reg mask_registers[] __initdata = {
|
||||
{ 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
|
||||
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
|
||||
{ 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
|
||||
{ IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
|
||||
IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
|
||||
IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
|
||||
IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
|
||||
IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
|
||||
IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
|
||||
IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
|
||||
IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
|
||||
|
||||
{ 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, DMAC1_8, 0, PECI0I, LPC, FRT, WDT1, TMR45,
|
||||
TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0,
|
||||
HUDI, 0, WDT0, SCIF3, SCIF2, SDHI, TMU345, TMU012
|
||||
} },
|
||||
|
||||
{ 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
|
||||
{ IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC,
|
||||
IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1,
|
||||
ADC1, 0, DMAC1_6, ADC0, SPI0, SIM, PECI2I, PECI1I,
|
||||
ARC4, 0, SPI1, JMC, 0, 0, 0, DVC
|
||||
} },
|
||||
|
||||
{ 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */
|
||||
{ IIC4_1, IIC4_2, IIC5_0, 0, 0, 0, SGPIO, 0,
|
||||
0, 0, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3,
|
||||
IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1,
|
||||
IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, PCIE, IIC2_2
|
||||
} },
|
||||
|
||||
{ 0xffd100d0, 0xff1400d4, 32, /* INT2MSKR3 / INT2MSKCR4 */
|
||||
{ 0, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, 0, 0,
|
||||
IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2,
|
||||
PCIINTA, 0, IIC4_0, 0, 0, 0, 0, IIC9_3,
|
||||
IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1
|
||||
} },
|
||||
};
|
||||
|
||||
#define INTPRI 0xffd00010
|
||||
#define INT2PRI0 0xffd40000
|
||||
#define INT2PRI1 0xffd40004
|
||||
#define INT2PRI2 0xffd40008
|
||||
#define INT2PRI3 0xffd4000c
|
||||
#define INT2PRI4 0xffd40010
|
||||
#define INT2PRI5 0xffd40014
|
||||
#define INT2PRI6 0xffd40018
|
||||
#define INT2PRI7 0xffd4001c
|
||||
#define INT2PRI8 0xffd400a0
|
||||
#define INT2PRI9 0xffd400a4
|
||||
#define INT2PRI10 0xffd400a8
|
||||
#define INT2PRI11 0xffd400ac
|
||||
#define INT2PRI12 0xffd400b0
|
||||
#define INT2PRI13 0xffd400b4
|
||||
#define INT2PRI14 0xffd400b8
|
||||
#define INT2PRI15 0xffd400bc
|
||||
#define INT2PRI16 0xffd10000
|
||||
#define INT2PRI17 0xffd10004
|
||||
#define INT2PRI18 0xffd10008
|
||||
#define INT2PRI19 0xffd1000c
|
||||
#define INT2PRI20 0xffd10010
|
||||
#define INT2PRI21 0xffd10014
|
||||
#define INT2PRI22 0xffd10018
|
||||
#define INT2PRI23 0xffd1001c
|
||||
#define INT2PRI24 0xffd100a0
|
||||
#define INT2PRI25 0xffd100a4
|
||||
#define INT2PRI26 0xffd100a8
|
||||
#define INT2PRI27 0xffd100ac
|
||||
#define INT2PRI28 0xffd100b0
|
||||
#define INT2PRI29 0xffd100b4
|
||||
#define INT2PRI30 0xffd100b8
|
||||
#define INT2PRI31 0xffd100bc
|
||||
|
||||
static struct intc_prio_reg prio_registers[] __initdata = {
|
||||
{ INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3,
|
||||
IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
|
||||
{ INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } },
|
||||
{ INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } },
|
||||
{ INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, WDT0, IRQ8 } },
|
||||
{ INT2PRI3, 0, 32, 8, { HUDI, DMAC0, ADC0, IRQ9 } },
|
||||
{ INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } },
|
||||
{ INT2PRI5, 0, 32, 8, { TMR45, WDT1, FRT, LPC } },
|
||||
{ INT2PRI6, 0, 32, 8, { PECI0I, ETHERC, DMAC1_8, 0 } },
|
||||
{ INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } },
|
||||
{ INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } },
|
||||
{ INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } },
|
||||
{ INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2I, PECI1I } },
|
||||
{ INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC1_6, IRQ14 } },
|
||||
{ INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } },
|
||||
{ INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } },
|
||||
|
||||
{ INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } },
|
||||
{ INT2PRI17, 0, 32, 8, { PCIE, 0, 0, IIC1_0 } },
|
||||
{ INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } },
|
||||
{ INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } },
|
||||
{ INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } },
|
||||
{ INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } },
|
||||
{ INT2PRI22, 0, 32, 8, { IIC9_2, 0, 0, 0 } },
|
||||
{ INT2PRI23, 0, 32, 8, { 0, SGPIO, IIC3_2, IIC5_1 } },
|
||||
{ INT2PRI24, 0, 32, 8, { 0, 0, 0, IIC1_1 } },
|
||||
{ INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } },
|
||||
{ INT2PRI26, 0, 32, 8, { 0, 0, 0, IIC9_3 } },
|
||||
{ INT2PRI27, 0, 32, 8, { PCIINTA, IIC6_0, IIC4_0, IIC6_1 } },
|
||||
{ INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, 0, IIC6_2 } },
|
||||
{ INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } },
|
||||
{ INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, 0 } },
|
||||
{ INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } },
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups,
|
||||
mask_registers, prio_registers, NULL);
|
||||
|
||||
/* Support for external interrupt pins in IRQ mode */
|
||||
static struct intc_vect vectors_irq0123[] __initdata = {
|
||||
INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
|
||||
INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
|
||||
};
|
||||
|
||||
static struct intc_vect vectors_irq4567[] __initdata = {
|
||||
INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
|
||||
INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
|
||||
};
|
||||
|
||||
static struct intc_sense_reg sense_registers[] __initdata = {
|
||||
{ 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
|
||||
IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
};
|
||||
|
||||
static struct intc_mask_reg ack_registers[] __initdata = {
|
||||
{ 0xffd00024, 0, 32, /* INTREQ */
|
||||
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7757-irq0123",
|
||||
vectors_irq0123, NULL, mask_registers,
|
||||
prio_registers, sense_registers, ack_registers);
|
||||
|
||||
static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7757-irq4567",
|
||||
vectors_irq4567, NULL, mask_registers,
|
||||
prio_registers, sense_registers, ack_registers);
|
||||
|
||||
/* External interrupt pins in IRL mode */
|
||||
static struct intc_vect vectors_irl0123[] __initdata = {
|
||||
INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
|
||||
INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
|
||||
INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
|
||||
INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
|
||||
INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
|
||||
INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
|
||||
INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
|
||||
INTC_VECT(IRL0_HHHL, 0x3c0),
|
||||
};
|
||||
|
||||
static struct intc_vect vectors_irl4567[] __initdata = {
|
||||
INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
|
||||
INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
|
||||
INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
|
||||
INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
|
||||
INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
|
||||
INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
|
||||
INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
|
||||
INTC_VECT(IRL4_HHHL, 0xcc0),
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7757-irl0123", vectors_irl0123,
|
||||
NULL, mask_registers, NULL, NULL);
|
||||
|
||||
static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567,
|
||||
NULL, mask_registers, NULL, NULL);
|
||||
|
||||
#define INTC_ICR0 0xffd00000
|
||||
#define INTC_INTMSK0 0xffd00044
|
||||
#define INTC_INTMSK1 0xffd00048
|
||||
#define INTC_INTMSK2 0xffd40080
|
||||
#define INTC_INTMSKCLR1 0xffd00068
|
||||
#define INTC_INTMSKCLR2 0xffd40084
|
||||
|
||||
void __init plat_irq_setup(void)
|
||||
{
|
||||
/* disable IRQ3-0 + IRQ7-4 */
|
||||
ctrl_outl(0xff000000, INTC_INTMSK0);
|
||||
|
||||
/* disable IRL3-0 + IRL7-4 */
|
||||
ctrl_outl(0xc0000000, INTC_INTMSK1);
|
||||
ctrl_outl(0xfffefffe, INTC_INTMSK2);
|
||||
|
||||
/* select IRL mode for IRL3-0 + IRL7-4 */
|
||||
ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
|
||||
|
||||
/* disable holding function, ie enable "SH-4 Mode" */
|
||||
ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
|
||||
|
||||
register_intc_controller(&intc_desc);
|
||||
}
|
||||
|
||||
void __init plat_irq_setup_pins(int mode)
|
||||
{
|
||||
switch (mode) {
|
||||
case IRQ_MODE_IRQ7654:
|
||||
/* select IRQ mode for IRL7-4 */
|
||||
ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
|
||||
register_intc_controller(&intc_desc_irq4567);
|
||||
break;
|
||||
case IRQ_MODE_IRQ3210:
|
||||
/* select IRQ mode for IRL3-0 */
|
||||
ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
|
||||
register_intc_controller(&intc_desc_irq0123);
|
||||
break;
|
||||
case IRQ_MODE_IRL7654:
|
||||
/* enable IRL7-4 but don't provide any masking */
|
||||
ctrl_outl(0x40000000, INTC_INTMSKCLR1);
|
||||
ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
|
||||
break;
|
||||
case IRQ_MODE_IRL3210:
|
||||
/* enable IRL0-3 but don't provide any masking */
|
||||
ctrl_outl(0x80000000, INTC_INTMSKCLR1);
|
||||
ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
|
||||
break;
|
||||
case IRQ_MODE_IRL7654_MASK:
|
||||
/* enable IRL7-4 and mask using cpu intc controller */
|
||||
ctrl_outl(0x40000000, INTC_INTMSKCLR1);
|
||||
register_intc_controller(&intc_desc_irl4567);
|
||||
break;
|
||||
case IRQ_MODE_IRL3210_MASK:
|
||||
/* enable IRL0-3 and mask using cpu intc controller */
|
||||
ctrl_outl(0x80000000, INTC_INTMSKCLR1);
|
||||
register_intc_controller(&intc_desc_irl0123);
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
}
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
}
|
||||
|
|
@ -481,7 +481,7 @@ static const char *cpu_name[] = {
|
|||
[CPU_SH7763] = "SH7763", [CPU_SH7770] = "SH7770",
|
||||
[CPU_SH7780] = "SH7780", [CPU_SH7781] = "SH7781",
|
||||
[CPU_SH7343] = "SH7343", [CPU_SH7785] = "SH7785",
|
||||
[CPU_SH7786] = "SH7786",
|
||||
[CPU_SH7786] = "SH7786", [CPU_SH7757] = "SH7757",
|
||||
[CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3",
|
||||
[CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103",
|
||||
[CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723",
|
||||
|
|
|
|||
|
|
@ -82,7 +82,7 @@ config 32BIT
|
|||
|
||||
config PMB_ENABLE
|
||||
bool "Support 32-bit physical addressing through PMB"
|
||||
depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
|
||||
depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7757 || CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
|
||||
select 32BIT
|
||||
default y
|
||||
help
|
||||
|
|
@ -97,7 +97,7 @@ choice
|
|||
|
||||
config PMB
|
||||
bool "PMB"
|
||||
depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
|
||||
depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7757 || CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
|
||||
select 32BIT
|
||||
help
|
||||
If you say Y here, physical addressing will be extended to
|
||||
|
|
@ -106,7 +106,8 @@ config PMB
|
|||
|
||||
config PMB_FIXED
|
||||
bool "fixed PMB"
|
||||
depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7780 || \
|
||||
depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7757 || \
|
||||
CPU_SUBTYPE_SH7780 || \
|
||||
CPU_SUBTYPE_SH7785)
|
||||
select 32BIT
|
||||
help
|
||||
|
|
|
|||
|
|
@ -272,7 +272,8 @@ static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
|
|||
__raw_writew(data, PSCR);
|
||||
}
|
||||
}
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7763) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7785) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7786) || \
|
||||
|
|
|
|||
|
|
@ -112,6 +112,13 @@
|
|||
#elif defined(CONFIG_H8S2678)
|
||||
# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
|
||||
# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
|
||||
# define SCSPTR0 0xfe4b0020
|
||||
# define SCSPTR1 0xfe4b0020
|
||||
# define SCSPTR2 0xfe4b0020
|
||||
# define SCIF_ORER 0x0001
|
||||
# define SCSCR_INIT(port) 0x38
|
||||
# define SCIF_ONLY
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
|
||||
# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
|
||||
# define SCSPTR1 0xffe08024 /* 16 bit SCIF */
|
||||
|
|
@ -562,6 +569,16 @@ static inline int sci_rxd_in(struct uart_port *port)
|
|||
return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
|
||||
return 1;
|
||||
}
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
if (port->mapbase == 0xfe4b0000)
|
||||
return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0;
|
||||
if (port->mapbase == 0xfe4c0000)
|
||||
return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0;
|
||||
if (port->mapbase == 0xfe4d0000)
|
||||
return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0;
|
||||
}
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
|
|
|
|||
Reference in New Issue