[CPUFREQ] EXYNOS5250: Add support max 1.7GHz for EXYNOS5250
This patch adds support 1.7GHz max frequency for EXYNOS5250 Signed-off-by: Jaecheol Lee <jc.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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@ -65,20 +65,20 @@ static unsigned int clkdiv_cpu0_5250[CPUFREQ_LEVEL_END][8] = {
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* Clock divider value for following
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* Clock divider value for following
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* { ARM, CPUD, ACP, PERIPH, ATB, PCLK_DBG, APLL, ARM2 }
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* { ARM, CPUD, ACP, PERIPH, ATB, PCLK_DBG, APLL, ARM2 }
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*/
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*/
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{ 0, 3, 7, 7, 6, 1, 3, 0 }, /* 1700 MHz - N/A */
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{ 0, 3, 7, 7, 7, 3, 5, 0 }, /* 1700 MHz */
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{ 0, 3, 7, 7, 6, 1, 3, 0 }, /* 1600 MHz - N/A */
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{ 0, 3, 7, 7, 7, 1, 4, 0 }, /* 1600 MHz */
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{ 0, 3, 7, 7, 5, 1, 3, 0 }, /* 1500 MHz - N/A */
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{ 0, 2, 7, 7, 7, 1, 4, 0 }, /* 1500 MHz */
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{ 0, 3, 7, 7, 6, 1, 3, 0 }, /* 1400 MHz */
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{ 0, 2, 7, 7, 6, 1, 4, 0 }, /* 1400 MHz */
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{ 0, 3, 7, 7, 6, 1, 3, 0 }, /* 1300 MHz */
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{ 0, 2, 7, 7, 6, 1, 3, 0 }, /* 1300 MHz */
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{ 0, 3, 7, 7, 5, 1, 3, 0 }, /* 1200 MHz */
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{ 0, 2, 7, 7, 5, 1, 3, 0 }, /* 1200 MHz */
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{ 0, 2, 7, 7, 5, 1, 2, 0 }, /* 1100 MHz */
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{ 0, 3, 7, 7, 5, 1, 3, 0 }, /* 1100 MHz */
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{ 0, 2, 7, 7, 4, 1, 2, 0 }, /* 1000 MHz */
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{ 0, 1, 7, 7, 4, 1, 2, 0 }, /* 1000 MHz */
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{ 0, 2, 7, 7, 4, 1, 2, 0 }, /* 900 MHz */
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{ 0, 1, 7, 7, 4, 1, 2, 0 }, /* 900 MHz */
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{ 0, 2, 7, 7, 3, 1, 1, 0 }, /* 800 MHz */
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{ 0, 1, 7, 7, 4, 1, 2, 0 }, /* 800 MHz */
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{ 0, 1, 7, 7, 3, 1, 1, 0 }, /* 700 MHz */
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{ 0, 1, 7, 7, 3, 1, 1, 0 }, /* 700 MHz */
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{ 0, 1, 7, 7, 2, 1, 1, 0 }, /* 600 MHz */
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{ 0, 1, 7, 7, 3, 1, 1, 0 }, /* 600 MHz */
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{ 0, 1, 7, 7, 2, 1, 1, 0 }, /* 500 MHz */
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{ 0, 1, 7, 7, 2, 1, 1, 0 }, /* 500 MHz */
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{ 0, 1, 7, 7, 1, 1, 1, 0 }, /* 400 MHz */
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{ 0, 1, 7, 7, 2, 1, 1, 0 }, /* 400 MHz */
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{ 0, 1, 7, 7, 1, 1, 1, 0 }, /* 300 MHz */
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{ 0, 1, 7, 7, 1, 1, 1, 0 }, /* 300 MHz */
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{ 0, 1, 7, 7, 1, 1, 1, 0 }, /* 200 MHz */
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{ 0, 1, 7, 7, 1, 1, 1, 0 }, /* 200 MHz */
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};
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};
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@ -87,9 +87,9 @@ static unsigned int clkdiv_cpu1_5250[CPUFREQ_LEVEL_END][2] = {
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/* Clock divider value for following
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/* Clock divider value for following
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* { COPY, HPM }
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* { COPY, HPM }
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*/
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*/
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{ 0, 2 }, /* 1700 MHz - N/A */
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{ 0, 2 }, /* 1700 MHz */
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{ 0, 2 }, /* 1600 MHz - N/A */
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{ 0, 2 }, /* 1600 MHz */
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{ 0, 2 }, /* 1500 MHz - N/A */
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{ 0, 2 }, /* 1500 MHz */
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{ 0, 2 }, /* 1400 MHz */
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{ 0, 2 }, /* 1400 MHz */
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{ 0, 2 }, /* 1300 MHz */
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{ 0, 2 }, /* 1300 MHz */
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{ 0, 2 }, /* 1200 MHz */
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{ 0, 2 }, /* 1200 MHz */
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@ -106,10 +106,10 @@ static unsigned int clkdiv_cpu1_5250[CPUFREQ_LEVEL_END][2] = {
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};
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};
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static unsigned int exynos5_apll_pms_table[CPUFREQ_LEVEL_END] = {
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static unsigned int exynos5_apll_pms_table[CPUFREQ_LEVEL_END] = {
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(0), /* 1700 MHz - N/A */
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((425 << 16) | (6 << 8) | 0), /* 1700 MHz */
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(0), /* 1600 MHz - N/A */
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((200 << 16) | (3 << 8) | 0), /* 1600 MHz */
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(0), /* 1500 MHz - N/A */
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((250 << 16) | (4 << 8) | 0), /* 1500 MHz */
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(0), /* 1400 MHz */
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((175 << 16) | (3 << 8) | 0), /* 1400 MHz */
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((325 << 16) | (6 << 8) | 0), /* 1300 MHz */
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((325 << 16) | (6 << 8) | 0), /* 1300 MHz */
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((200 << 16) | (4 << 8) | 0), /* 1200 MHz */
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((200 << 16) | (4 << 8) | 0), /* 1200 MHz */
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((275 << 16) | (6 << 8) | 0), /* 1100 MHz */
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((275 << 16) | (6 << 8) | 0), /* 1100 MHz */
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@ -126,9 +126,10 @@ static unsigned int exynos5_apll_pms_table[CPUFREQ_LEVEL_END] = {
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/* ASV group voltage table */
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/* ASV group voltage table */
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static const unsigned int asv_voltage_5250[CPUFREQ_LEVEL_END] = {
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static const unsigned int asv_voltage_5250[CPUFREQ_LEVEL_END] = {
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0, 0, 0, 0, 0, 0, 0, /* 1700 MHz ~ 1100 MHz Not supported */
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1300000, 1250000, 1225000, 1200000, 1150000,
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1175000, 1125000, 1075000, 1050000, 1000000,
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1125000, 1100000, 1075000, 1050000, 1025000,
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950000, 925000, 925000, 900000
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1012500, 1000000, 975000, 950000, 937500,
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925000
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};
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};
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static void set_clkdiv(unsigned int div_index)
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static void set_clkdiv(unsigned int div_index)
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@ -248,15 +249,7 @@ static void __init set_volt_table(void)
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{
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{
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unsigned int i;
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unsigned int i;
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exynos5250_freq_table[L0].frequency = CPUFREQ_ENTRY_INVALID;
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max_support_idx = L0;
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exynos5250_freq_table[L1].frequency = CPUFREQ_ENTRY_INVALID;
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exynos5250_freq_table[L2].frequency = CPUFREQ_ENTRY_INVALID;
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exynos5250_freq_table[L3].frequency = CPUFREQ_ENTRY_INVALID;
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exynos5250_freq_table[L4].frequency = CPUFREQ_ENTRY_INVALID;
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exynos5250_freq_table[L5].frequency = CPUFREQ_ENTRY_INVALID;
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exynos5250_freq_table[L6].frequency = CPUFREQ_ENTRY_INVALID;
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max_support_idx = L7;
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for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++)
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for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++)
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exynos5250_volt_table[i] = asv_voltage_5250[i];
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exynos5250_volt_table[i] = asv_voltage_5250[i];
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