blackfin: add bf60x to current framework
This patch added bf60x to current blackfin kernel framework. Signed-off-by: Bob Liu <lliubbo@gmail.com>
This commit is contained in:
Bob Liu
parent
22a8262885
commit
b5affb0147
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@ -226,6 +226,12 @@ config BF561
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help
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BF561 Processor Support.
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config BF609
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bool "BF609"
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select CLKDEV_LOOKUP
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help
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BF609 Processor Support.
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endchoice
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config SMP
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@ -251,27 +257,27 @@ config HOTPLUG_CPU
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config BF_REV_MIN
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int
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default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
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default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
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default 2 if (BF537 || BF536 || BF534)
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default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
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default 4 if (BF538 || BF539)
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config BF_REV_MAX
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int
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default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
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default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
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default 3 if (BF537 || BF536 || BF534 || BF54xM)
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default 5 if (BF561 || BF538 || BF539)
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default 6 if (BF533 || BF532 || BF531)
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choice
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prompt "Silicon Rev"
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default BF_REV_0_0 if (BF51x || BF52x)
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default BF_REV_0_0 if (BF51x || BF52x || BF60x)
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default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
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default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
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config BF_REV_0_0
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bool "0.0"
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depends on (BF51x || BF52x || (BF54x && !BF54xM))
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depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
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config BF_REV_0_1
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bool "0.1"
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@ -350,6 +356,7 @@ source "arch/blackfin/mach-bf561/Kconfig"
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source "arch/blackfin/mach-bf537/Kconfig"
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source "arch/blackfin/mach-bf538/Kconfig"
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source "arch/blackfin/mach-bf548/Kconfig"
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source "arch/blackfin/mach-bf609/Kconfig"
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menu "Board customizations"
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@ -379,6 +386,12 @@ config BOOT_LOAD
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memory region is used to capture NULL pointer references as well
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as some core kernel functions.
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config PHY_RAM_BASE_ADDRESS
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hex "Physical RAM Base"
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default 0x0
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help
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set BF609 FPGA physical SRAM base address
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config ROM_BASE
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hex "Kernel ROM Base"
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depends on ROMKERNEL
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@ -1051,7 +1064,7 @@ endchoice
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config BFIN_L2_DCACHEABLE
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bool "Enable DCACHE for L2 SRAM"
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depends on BFIN_DCACHE
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depends on (BF54x || BF561) && !SMP
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depends on (BF54x || BF561 || BF60x) && !SMP
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default n
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choice
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prompt "L2 SRAM DCACHE policy"
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@ -1077,6 +1090,7 @@ config MPU
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comment "Asynchronous Memory Configuration"
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menu "EBIU_AMGCTL Global Control"
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depends on !BF60x
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config C_AMCKEN
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bool "Enable CLKOUT"
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default y
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@ -1127,6 +1141,7 @@ endchoice
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endmenu
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menu "EBIU_AMBCTL Control"
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depends on !BF60x
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config BANK_0
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hex "Bank 0 (AMBCTL0.L)"
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default 0x7BB0
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@ -54,6 +54,7 @@ machine-$(CONFIG_BF548M) := bf548
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machine-$(CONFIG_BF549) := bf548
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machine-$(CONFIG_BF549M) := bf548
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machine-$(CONFIG_BF561) := bf561
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machine-$(CONFIG_BF609) := bf609
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MACHINE := $(machine-y)
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export MACHINE
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@ -86,6 +87,7 @@ cpu-$(CONFIG_BF548M) := bf548m
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cpu-$(CONFIG_BF549) := bf549
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cpu-$(CONFIG_BF549M) := bf549m
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cpu-$(CONFIG_BF561) := bf561
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cpu-$(CONFIG_BF609) := bf609
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rev-$(CONFIG_BF_REV_0_0) := 0.0
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rev-$(CONFIG_BF_REV_0_1) := 0.1
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@ -0,0 +1,153 @@
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CONFIG_EXPERIMENTAL=y
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CONFIG_SYSVIPC=y
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CONFIG_IKCONFIG=y
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CONFIG_IKCONFIG_PROC=y
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CONFIG_LOG_BUF_SHIFT=14
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CONFIG_BLK_DEV_INITRD=y
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CONFIG_EXPERT=y
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# CONFIG_ELF_CORE is not set
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# CONFIG_FUTEX is not set
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# CONFIG_SIGNALFD is not set
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# CONFIG_TIMERFD is not set
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# CONFIG_EVENTFD is not set
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# CONFIG_AIO is not set
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CONFIG_SLAB=y
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CONFIG_MMAP_ALLOW_UNINITIALIZED=y
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CONFIG_MODULES=y
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CONFIG_MODULE_UNLOAD=y
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# CONFIG_LBDAF is not set
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# CONFIG_BLK_DEV_BSG is not set
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# CONFIG_IOSCHED_DEADLINE is not set
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# CONFIG_IOSCHED_CFQ is not set
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CONFIG_PREEMPT_VOLUNTARY=y
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CONFIG_BF609=y
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CONFIG_PINT1_ASSIGN=0x01010000
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CONFIG_PINT2_ASSIGN=0x07000101
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CONFIG_PINT3_ASSIGN=0x02020303
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CONFIG_HIGH_RES_TIMERS=y
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CONFIG_IP_CHECKSUM_L1=y
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CONFIG_SYSCALL_TAB_L1=y
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CONFIG_CPLB_SWITCH_TAB_L1=y
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# CONFIG_APP_STACK_L1 is not set
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# CONFIG_BFIN_INS_LOWOVERHEAD is not set
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CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
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CONFIG_BINFMT_FLAT=y
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CONFIG_BINFMT_ZFLAT=y
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# CONFIG_SUSPEND is not set
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CONFIG_CPU_FREQ=y
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CONFIG_CPU_FREQ_GOV_POWERSAVE=y
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CONFIG_CPU_FREQ_GOV_ONDEMAND=y
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CONFIG_NET=y
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CONFIG_PACKET=y
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CONFIG_UNIX=y
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CONFIG_INET=y
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CONFIG_IP_PNP=y
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CONFIG_IP_PNP_DHCP=y
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CONFIG_IP_PNP_BOOTP=y
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CONFIG_IP_PNP_RARP=y
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# CONFIG_IPV6 is not set
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CONFIG_NETFILTER=y
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CONFIG_CAN=y
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CONFIG_CAN_BFIN=y
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CONFIG_IRDA=y
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CONFIG_IRTTY_SIR=y
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# CONFIG_WIRELESS is not set
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CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
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CONFIG_FW_LOADER=m
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CONFIG_MTD=y
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CONFIG_MTD_CMDLINE_PARTS=y
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CONFIG_MTD_CHAR=y
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CONFIG_MTD_CFI=y
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CONFIG_MTD_CFI_INTELEXT=y
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CONFIG_MTD_CFI_STAA=y
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CONFIG_MTD_COMPLEX_MAPPINGS=y
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CONFIG_MTD_BFIN_BF60x=y
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CONFIG_MTD_M25P80=y
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CONFIG_MTD_UBI=m
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CONFIG_SCSI=y
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CONFIG_BLK_DEV_SD=y
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CONFIG_NETDEVICES=y
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# CONFIG_NET_VENDOR_BROADCOM is not set
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# CONFIG_NET_VENDOR_CHELSIO is not set
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# CONFIG_NET_VENDOR_INTEL is not set
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# CONFIG_NET_VENDOR_MARVELL is not set
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# CONFIG_NET_VENDOR_MICREL is not set
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# CONFIG_NET_VENDOR_MICROCHIP is not set
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# CONFIG_NET_VENDOR_NATSEMI is not set
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# CONFIG_NET_VENDOR_SEEQ is not set
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# CONFIG_NET_VENDOR_SMSC is not set
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CONFIG_STMMAC_ETH=y
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CONFIG_STMMAC_IEEE1588=y
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# CONFIG_WLAN is not set
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# CONFIG_INPUT_MOUSEDEV is not set
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CONFIG_INPUT_EVDEV=y
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# CONFIG_INPUT_KEYBOARD is not set
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# CONFIG_INPUT_MOUSE is not set
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CONFIG_INPUT_MISC=y
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CONFIG_INPUT_BFIN_ROTARY=y
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# CONFIG_SERIO is not set
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# CONFIG_LEGACY_PTYS is not set
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CONFIG_BFIN_SIMPLE_TIMER=m
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CONFIG_BFIN_LINKPORT=y
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# CONFIG_DEVKMEM is not set
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CONFIG_SERIAL_BFIN=y
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CONFIG_SERIAL_BFIN_CONSOLE=y
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CONFIG_SERIAL_BFIN_UART0=y
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# CONFIG_HW_RANDOM is not set
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CONFIG_I2C=y
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CONFIG_I2C_CHARDEV=y
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CONFIG_I2C_BLACKFIN_TWI=y
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CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
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CONFIG_SPI=y
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CONFIG_SPI_BFIN6XX=y
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CONFIG_GPIOLIB=y
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CONFIG_GPIO_SYSFS=y
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# CONFIG_HWMON is not set
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CONFIG_WATCHDOG=y
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CONFIG_BFIN_WDT=y
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CONFIG_SOUND=m
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CONFIG_SND=m
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CONFIG_SND_MIXER_OSS=m
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CONFIG_SND_PCM_OSS=m
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# CONFIG_SND_DRIVERS is not set
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# CONFIG_SND_SPI is not set
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# CONFIG_SND_USB is not set
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CONFIG_SND_SOC=m
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CONFIG_SND_BF6XX_I2S=m
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CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61=m
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CONFIG_SND_SOC_ALL_CODECS=m
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CONFIG_USB=y
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CONFIG_USB_MUSB_HDRC=y
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CONFIG_USB_MUSB_BLACKFIN=y
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CONFIG_USB_STORAGE=y
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CONFIG_USB_GADGET=y
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CONFIG_USB_GADGET_MUSB_HDRC=y
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CONFIG_USB_ZERO=y
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CONFIG_MMC=y
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CONFIG_SDH_BFIN=y
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# CONFIG_IOMMU_SUPPORT is not set
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CONFIG_EXT2_FS=y
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# CONFIG_DNOTIFY is not set
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CONFIG_MSDOS_FS=y
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CONFIG_VFAT_FS=y
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CONFIG_JFFS2_FS=m
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CONFIG_UBIFS_FS=m
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CONFIG_NFS_FS=m
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CONFIG_NFS_V3=y
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CONFIG_NLS_CODEPAGE_437=y
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CONFIG_NLS_ISO8859_1=y
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CONFIG_DEBUG_FS=y
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CONFIG_DEBUG_SHIRQ=y
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CONFIG_DETECT_HUNG_TASK=y
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CONFIG_DEBUG_INFO=y
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CONFIG_FRAME_POINTER=y
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# CONFIG_FTRACE is not set
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CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
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CONFIG_EARLY_PRINTK=y
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CONFIG_CPLB_INFO=y
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CONFIG_BFIN_PSEUDODBG_INSNS=y
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CONFIG_CRYPTO_HMAC=y
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CONFIG_CRYPTO_MD4=y
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CONFIG_CRYPTO_MD5=y
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CONFIG_CRYPTO_ARC4=y
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# CONFIG_CRYPTO_ANSI_CPRNG is not set
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@ -35,6 +35,11 @@ extern void bfin_setup_cpudata(unsigned int cpu);
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extern unsigned long get_cclk(void);
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extern unsigned long get_sclk(void);
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#ifdef CONFIG_BF60x
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extern unsigned long get_sclk0(void);
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extern unsigned long get_sclk1(void);
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extern unsigned long get_dramclk(void);
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#endif
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extern unsigned long sclk_to_usecs(unsigned long sclk);
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extern unsigned long usecs_to_sclk(unsigned long usecs);
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@ -15,12 +15,55 @@
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#define DMAEN 0x0001 /* DMA Channel Enable */
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#define WNR 0x0002 /* Channel Direction (W/R*) */
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#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
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#define PSIZE_8 0x00000000 /* Transfer Word Size = 16 */
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#ifdef CONFIG_BF60x
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#define PSIZE_16 0x00000010 /* Transfer Word Size = 16 */
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#define PSIZE_32 0x00000020 /* Transfer Word Size = 32 */
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#define PSIZE_64 0x00000030 /* Transfer Word Size = 32 */
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#define WDSIZE_16 0x00000100 /* Transfer Word Size = 16 */
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#define WDSIZE_32 0x00000200 /* Transfer Word Size = 32 */
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#define WDSIZE_64 0x00000300 /* Transfer Word Size = 32 */
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#define WDSIZE_128 0x00000400 /* Transfer Word Size = 32 */
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#define WDSIZE_256 0x00000500 /* Transfer Word Size = 32 */
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#define DMA2D 0x04000000 /* DMA Mode (2D/1D*) */
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#define RESTART 0x00000004 /* DMA Buffer Clear SYNC */
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#define DI_EN_X 0x00100000 /* Data Interrupt Enable in X count */
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#define DI_EN_Y 0x00200000 /* Data Interrupt Enable in Y count */
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#define DI_EN_P 0x00300000 /* Data Interrupt Enable in Peripheral */
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#define DI_EN DI_EN_X /* Data Interrupt Enable */
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#define NDSIZE_0 0x00000000 /* Next Descriptor Size = 1 */
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#define NDSIZE_1 0x00010000 /* Next Descriptor Size = 2 */
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#define NDSIZE_2 0x00020000 /* Next Descriptor Size = 3 */
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#define NDSIZE_3 0x00030000 /* Next Descriptor Size = 4 */
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#define NDSIZE_4 0x00040000 /* Next Descriptor Size = 5 */
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#define NDSIZE_5 0x00050000 /* Next Descriptor Size = 6 */
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#define NDSIZE_6 0x00060000 /* Next Descriptor Size = 7 */
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#define NDSIZE 0x00070000 /* Next Descriptor Size */
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#define NDSIZE_OFFSET 16 /* Next Descriptor Size Offset */
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#define DMAFLOW_LIST 0x00004000 /* Descriptor List Mode */
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#define DMAFLOW_LARGE DMAFLOW_LIST
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#define DMAFLOW_ARRAY 0x00005000 /* Descriptor Array Mode */
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#define DMAFLOW_LIST_DEMAND 0x00006000 /* Descriptor Demand List Mode */
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#define DMAFLOW_ARRAY_DEMAND 0x00007000 /* Descriptor Demand Array Mode */
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#define DMA_RUN_DFETCH 0x00000100 /* DMA Channel Running Indicator (DFETCH) */
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#define DMA_RUN 0x00000200 /* DMA Channel Running Indicator */
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#define DMA_RUN_WAIT_TRIG 0x00000300 /* DMA Channel Running Indicator (WAIT TRIG) */
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#define DMA_RUN_WAIT_ACK 0x00000400 /* DMA Channel Running Indicator (WAIT ACK) */
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#else
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#define PSIZE_16 0x0000 /* Transfer Word Size = 16 */
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#define PSIZE_32 0x0000 /* Transfer Word Size = 32 */
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#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
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#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
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#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
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#define RESTART 0x0020 /* DMA Buffer Clear */
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#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
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#define DI_EN 0x0080 /* Data Interrupt Enable */
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#define DI_EN_X 0x00C0 /* Data Interrupt Enable in X count*/
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#define DI_EN_Y 0x0080 /* Data Interrupt Enable in Y count*/
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#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
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#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
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#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
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@ -32,18 +75,26 @@
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#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
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#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
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#define NDSIZE 0x0f00 /* Next Descriptor Size */
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#define DMAFLOW 0x7000 /* Flow Control */
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#define DMAFLOW_STOP 0x0000 /* Stop Mode */
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#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
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#define NDSIZE_OFFSET 8 /* Next Descriptor Size Offset */
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#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
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#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
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#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
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#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
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#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
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#endif
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#define DMAFLOW 0x7000 /* Flow Control */
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#define DMAFLOW_STOP 0x0000 /* Stop Mode */
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#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
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/* DMA_IRQ_STATUS Masks */
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#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
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#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
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#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
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#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
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#ifdef CONFIG_BF60x
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#define DMA_PIRQ 0x0004 /* DMA Peripheral Error Interrupt Status */
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#else
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#define DMA_PIRQ 0
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#endif
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/*
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* All Blackfin system MMRs are padded to 32bits even if the register
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@ -57,6 +108,26 @@
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struct bfin_dma_regs {
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u32 next_desc_ptr;
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u32 start_addr;
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#ifdef CONFIG_BF60x
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u32 cfg;
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u32 x_count;
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u32 x_modify;
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u32 y_count;
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u32 y_modify;
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u32 pad1;
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u32 pad2;
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u32 curr_desc_ptr;
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u32 prev_desc_ptr;
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u32 curr_addr;
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u32 irq_status;
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u32 curr_x_count;
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u32 curr_y_count;
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u32 pad3;
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u32 bw_limit_count;
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u32 curr_bw_limit_count;
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u32 bw_monitor_count;
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u32 curr_bw_monitor_count;
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#else
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__BFP(config);
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u32 __pad0;
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__BFP(x_count);
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@ -71,8 +142,10 @@ struct bfin_dma_regs {
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u32 __pad1;
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__BFP(curr_y_count);
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u32 __pad2;
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#endif
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};
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#ifndef CONFIG_BF60x
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/*
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* bfin handshake mdma registers layout
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*/
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@ -85,6 +158,7 @@ struct bfin_hmdma_regs {
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__BFP(ecount);
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__BFP(bcount);
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};
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#endif
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#undef __BFP
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@ -18,7 +18,7 @@
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defined(CONFIG_BFIN_UART1_CTSRTS) || \
|
||||
defined(CONFIG_BFIN_UART2_CTSRTS) || \
|
||||
defined(CONFIG_BFIN_UART3_CTSRTS)
|
||||
# ifdef BFIN_UART_BF54X_STYLE
|
||||
# if defined(BFIN_UART_BF54X_STYLE) || defined(BFIN_UART_BF60X_STYLE)
|
||||
# define CONFIG_SERIAL_BFIN_HARD_CTSRTS
|
||||
# else
|
||||
# define CONFIG_SERIAL_BFIN_CTSRTS
|
||||
|
|
@ -58,14 +58,67 @@ struct bfin_serial_port {
|
|||
#endif
|
||||
};
|
||||
|
||||
#ifdef BFIN_UART_BF60X_STYLE
|
||||
|
||||
/* UART_CTL Masks */
|
||||
#define UCEN 0x1 /* Enable UARTx Clocks */
|
||||
#define LOOP_ENA 0x2 /* Loopback Mode Enable */
|
||||
#define UMOD_MDB 0x10 /* Enable MDB Mode */
|
||||
#define UMOD_IRDA 0x20 /* Enable IrDA Mode */
|
||||
#define UMOD_MASK 0x30 /* Uart Mode Mask */
|
||||
#define WLS(x) (((x-5) & 0x03) << 8) /* Word Length Select */
|
||||
#define WLS_MASK 0x300 /* Word length Select Mask */
|
||||
#define STB 0x1000 /* Stop Bits */
|
||||
#define STBH 0x2000 /* Half Stop Bits */
|
||||
#define PEN 0x4000 /* Parity Enable */
|
||||
#define EPS 0x8000 /* Even Parity Select */
|
||||
#define STP 0x10000 /* Stick Parity */
|
||||
#define FPE 0x20000 /* Force Parity Error On Transmit */
|
||||
#define FFE 0x40000 /* Force Framing Error On Transmit */
|
||||
#define SB 0x80000 /* Set Break */
|
||||
#define LCR_MASK (STP | EPS | PEN | STB | WLS_MASK)
|
||||
#define FCPOL 0x400000 /* Flow Control Pin Polarity */
|
||||
#define RPOLC 0x800000 /* IrDA RX Polarity Change */
|
||||
#define TPOLC 0x1000000 /* IrDA TX Polarity Change */
|
||||
#define MRTS 0x2000000 /* Manual Request To Send */
|
||||
#define XOFF 0x4000000 /* Transmitter Off */
|
||||
#define ARTS 0x8000000 /* Automatic Request To Send */
|
||||
#define ACTS 0x10000000 /* Automatic Clear To Send */
|
||||
#define RFIT 0x20000000 /* Receive FIFO IRQ Threshold */
|
||||
#define RFRT 0x40000000 /* Receive FIFO RTS Threshold */
|
||||
|
||||
/* UART_STAT Masks */
|
||||
#define DR 0x01 /* Data Ready */
|
||||
#define OE 0x02 /* Overrun Error */
|
||||
#define PE 0x04 /* Parity Error */
|
||||
#define FE 0x08 /* Framing Error */
|
||||
#define BI 0x10 /* Break Interrupt */
|
||||
#define THRE 0x20 /* THR Empty */
|
||||
#define TEMT 0x80 /* TSR and UART_THR Empty */
|
||||
#define TFI 0x100 /* Transmission Finished Indicator */
|
||||
|
||||
#define ASTKY 0x200 /* Address Sticky */
|
||||
#define ADDR 0x400 /* Address bit status */
|
||||
#define RO 0x800 /* Reception Ongoing */
|
||||
#define SCTS 0x1000 /* Sticky CTS */
|
||||
#define CTS 0x10000 /* Clear To Send */
|
||||
#define RFCS 0x20000 /* Receive FIFO Count Status */
|
||||
|
||||
/* UART_CLOCK Masks */
|
||||
#define EDBO 0x80000000 /* Enable Devide by One */
|
||||
|
||||
#else /* BFIN_UART_BF60X_STYLE */
|
||||
|
||||
/* UART_LCR Masks */
|
||||
#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
|
||||
#define WLS_MASK 0x03 /* Word length Select Mask */
|
||||
#define STB 0x04 /* Stop Bits */
|
||||
#define PEN 0x08 /* Parity Enable */
|
||||
#define EPS 0x10 /* Even Parity Select */
|
||||
#define STP 0x20 /* Stick Parity */
|
||||
#define SB 0x40 /* Set Break */
|
||||
#define DLAB 0x80 /* Divisor Latch Access */
|
||||
#define LCR_MASK (STP | EPS | PEN | STB | WLS_MASK)
|
||||
|
||||
/* UART_LSR Masks */
|
||||
#define DR 0x01 /* Data Ready */
|
||||
|
|
@ -77,15 +130,6 @@ struct bfin_serial_port {
|
|||
#define TEMT 0x40 /* TSR and UART_THR Empty */
|
||||
#define TFI 0x80 /* Transmission Finished Indicator */
|
||||
|
||||
/* UART_IER Masks */
|
||||
#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
|
||||
#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
|
||||
#define ELSI 0x04 /* Enable RX Status Interrupt */
|
||||
#define EDSSI 0x08 /* Enable Modem Status Interrupt */
|
||||
#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
|
||||
#define ETFI 0x20 /* Enable Transmission Finished Interrupt */
|
||||
#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
|
||||
|
||||
/* UART_MCR Masks */
|
||||
#define XOFF 0x01 /* Transmitter Off */
|
||||
#define MRTS 0x02 /* Manual Request To Send */
|
||||
|
|
@ -103,13 +147,36 @@ struct bfin_serial_port {
|
|||
|
||||
/* UART_GCTL Masks */
|
||||
#define UCEN 0x01 /* Enable UARTx Clocks */
|
||||
#define IREN 0x02 /* Enable IrDA Mode */
|
||||
#define UMOD_IRDA 0x02 /* Enable IrDA Mode */
|
||||
#define UMOD_MASK 0x02 /* Uart Mode Mask */
|
||||
#define TPOLC 0x04 /* IrDA TX Polarity Change */
|
||||
#define RPOLC 0x08 /* IrDA RX Polarity Change */
|
||||
#define FPE 0x10 /* Force Parity Error On Transmit */
|
||||
#define FFE 0x20 /* Force Framing Error On Transmit */
|
||||
|
||||
#ifdef BFIN_UART_BF54X_STYLE
|
||||
#endif /* BFIN_UART_BF60X_STYLE */
|
||||
|
||||
/* UART_IER Masks */
|
||||
#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
|
||||
#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
|
||||
#define ELSI 0x04 /* Enable RX Status Interrupt */
|
||||
#define EDSSI 0x08 /* Enable Modem Status Interrupt */
|
||||
#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
|
||||
#define ETFI 0x20 /* Enable Transmission Finished Interrupt */
|
||||
#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
|
||||
|
||||
#if defined(BFIN_UART_BF60X_STYLE)
|
||||
# define OFFSET_REDIV 0x00 /* Version ID Register */
|
||||
# define OFFSET_CTL 0x04 /* Control Register */
|
||||
# define OFFSET_STAT 0x08 /* Status Register */
|
||||
# define OFFSET_SCR 0x0C /* SCR Scratch Register */
|
||||
# define OFFSET_CLK 0x10 /* Clock Rate Register */
|
||||
# define OFFSET_IER 0x14 /* Interrupt Enable Register */
|
||||
# define OFFSET_IER_SET 0x18 /* Set Interrupt Enable Register */
|
||||
# define OFFSET_IER_CLEAR 0x1C /* Clear Interrupt Enable Register */
|
||||
# define OFFSET_RBR 0x20 /* Receive Buffer register */
|
||||
# define OFFSET_THR 0x24 /* Transmit Holding register */
|
||||
#elif defined(BFIN_UART_BF54X_STYLE)
|
||||
# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
|
||||
# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
|
||||
# define OFFSET_GCTL 0x08 /* Global Control Register */
|
||||
|
|
@ -145,7 +212,23 @@ struct bfin_serial_port {
|
|||
*/
|
||||
#define __BFP(m) u16 m; u16 __pad_##m
|
||||
struct bfin_uart_regs {
|
||||
#ifdef BFIN_UART_BF54X_STYLE
|
||||
#if defined(BFIN_UART_BF60X_STYLE)
|
||||
u32 revid;
|
||||
u32 ctl;
|
||||
u32 stat;
|
||||
u32 scr;
|
||||
u32 clk;
|
||||
u32 ier;
|
||||
u32 ier_set;
|
||||
u32 ier_clear;
|
||||
u32 rbr;
|
||||
u32 thr;
|
||||
u32 taip;
|
||||
u32 tsr;
|
||||
u32 rsr;
|
||||
u32 txdiv;
|
||||
u32 rxdiv;
|
||||
#elif defined(BFIN_UART_BF54X_STYLE)
|
||||
__BFP(dll);
|
||||
__BFP(dlh);
|
||||
__BFP(gctl);
|
||||
|
|
@ -182,13 +265,58 @@ struct bfin_uart_regs {
|
|||
};
|
||||
#undef __BFP
|
||||
|
||||
#define port_membase(uart) (((struct bfin_serial_port *)(uart))->port.membase)
|
||||
|
||||
/*
|
||||
#ifndef port_membase
|
||||
# define port_membase(p) 0
|
||||
#endif
|
||||
*/
|
||||
#ifdef BFIN_UART_BF60X_STYLE
|
||||
|
||||
#define UART_GET_CHAR(p) bfin_read32(port_membase(p) + OFFSET_RBR)
|
||||
#define UART_GET_CLK(p) bfin_read32(port_membase(p) + OFFSET_CLK)
|
||||
#define UART_GET_CTL(p) bfin_read32(port_membase(p) + OFFSET_CTL)
|
||||
#define UART_GET_GCTL(p) UART_GET_CTL(p)
|
||||
#define UART_GET_LCR(p) UART_GET_CTL(p)
|
||||
#define UART_GET_MCR(p) UART_GET_CTL(p)
|
||||
#define UART_GET_STAT(p) bfin_read32(port_membase(p) + OFFSET_STAT)
|
||||
#define UART_GET_MSR(p) UART_GET_STAT(p)
|
||||
|
||||
#define UART_PUT_CHAR(p, v) bfin_write32(port_membase(p) + OFFSET_THR, v)
|
||||
#define UART_PUT_CLK(p, v) bfin_write32(port_membase(p) + OFFSET_CLK, v)
|
||||
#define UART_PUT_CTL(p, v) bfin_write32(port_membase(p) + OFFSET_CTL, v)
|
||||
#define UART_PUT_GCTL(p, v) UART_PUT_CTL(p, v)
|
||||
#define UART_PUT_LCR(p, v) UART_PUT_CTL(p, v)
|
||||
#define UART_PUT_MCR(p, v) UART_PUT_CTL(p, v)
|
||||
#define UART_PUT_STAT(p, v) bfin_write32(port_membase(p) + OFFSET_STAT, v)
|
||||
|
||||
#define UART_CLEAR_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_CLEAR, v)
|
||||
#define UART_GET_IER(p) bfin_read32(port_membase(p) + OFFSET_IER)
|
||||
#define UART_SET_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_SET, v)
|
||||
|
||||
#define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF60x */
|
||||
#define UART_SET_DLAB(p) /* MMRs not muxed on BF60x */
|
||||
|
||||
#define UART_CLEAR_LSR(p) UART_PUT_STAT(p, -1)
|
||||
#define UART_GET_LSR(p) UART_GET_STAT(p)
|
||||
#define UART_PUT_LSR(p, v) UART_PUT_STAT(p, v)
|
||||
|
||||
/* This handles hard CTS/RTS */
|
||||
#define BFIN_UART_CTSRTS_HARD
|
||||
#define UART_CLEAR_SCTS(p) UART_PUT_STAT(p, SCTS)
|
||||
#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
|
||||
#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
|
||||
#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
|
||||
#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
|
||||
#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
|
||||
|
||||
#else /* BFIN_UART_BF60X_STYLE */
|
||||
|
||||
#define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR)
|
||||
#define UART_GET_DLL(p) bfin_read16(port_membase(p) + OFFSET_DLL)
|
||||
#define UART_GET_DLH(p) bfin_read16(port_membase(p) + OFFSET_DLH)
|
||||
#define UART_GET_CLK(p) ((UART_GET_DLH(p) << 8) | UART_GET_DLL(p))
|
||||
#define UART_GET_GCTL(p) bfin_read16(port_membase(p) + OFFSET_GCTL)
|
||||
#define UART_GET_LCR(p) bfin_read16(port_membase(p) + OFFSET_LCR)
|
||||
#define UART_GET_MCR(p) bfin_read16(port_membase(p) + OFFSET_MCR)
|
||||
|
|
@ -197,6 +325,11 @@ struct bfin_uart_regs {
|
|||
#define UART_PUT_CHAR(p, v) bfin_write16(port_membase(p) + OFFSET_THR, v)
|
||||
#define UART_PUT_DLL(p, v) bfin_write16(port_membase(p) + OFFSET_DLL, v)
|
||||
#define UART_PUT_DLH(p, v) bfin_write16(port_membase(p) + OFFSET_DLH, v)
|
||||
#define UART_PUT_CLK(p, v) do \
|
||||
{\
|
||||
UART_PUT_DLL(p, v & 0xFF); \
|
||||
UART_PUT_DLH(p, (v >> 8) & 0xFF); } while (0);
|
||||
|
||||
#define UART_PUT_GCTL(p, v) bfin_write16(port_membase(p) + OFFSET_GCTL, v)
|
||||
#define UART_PUT_LCR(p, v) bfin_write16(port_membase(p) + OFFSET_LCR, v)
|
||||
#define UART_PUT_MCR(p, v) bfin_write16(port_membase(p) + OFFSET_MCR, v)
|
||||
|
|
@ -233,12 +366,17 @@ struct bfin_uart_regs {
|
|||
#define UART_CLEAR_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0)
|
||||
#define UART_SET_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0)
|
||||
|
||||
#define get_lsr_cache(uart) (((struct bfin_serial_port *)(uart))->lsr)
|
||||
#define put_lsr_cache(uart, v) (((struct bfin_serial_port *)(uart))->lsr = (v))
|
||||
|
||||
/*
|
||||
#ifndef put_lsr_cache
|
||||
# define put_lsr_cache(p, v)
|
||||
#endif
|
||||
#ifndef get_lsr_cache
|
||||
# define get_lsr_cache(p) 0
|
||||
#endif
|
||||
*/
|
||||
|
||||
/* The hardware clears the LSR bits upon read, so we need to cache
|
||||
* some of the more fun bits in software so they don't get lost
|
||||
|
|
@ -267,7 +405,9 @@ static inline void UART_PUT_LSR(void *p, uint16_t val)
|
|||
#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
|
||||
#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
|
||||
|
||||
#endif
|
||||
#endif /* BFIN_UART_BF54X_STYLE */
|
||||
|
||||
#endif /* BFIN_UART_BF60X_STYLE */
|
||||
|
||||
#ifndef BFIN_UART_TX_FIFO_SIZE
|
||||
# define BFIN_UART_TX_FIFO_SIZE 2
|
||||
|
|
|
|||
|
|
@ -22,12 +22,22 @@
|
|||
#define DATA_SIZE_8 0
|
||||
#define DATA_SIZE_16 1
|
||||
#define DATA_SIZE_32 2
|
||||
#ifdef CONFIG_BF60x
|
||||
#define DATA_SIZE_64 3
|
||||
#endif
|
||||
|
||||
#define DMA_FLOW_STOP 0
|
||||
#define DMA_FLOW_AUTO 1
|
||||
#ifdef CONFIG_BF60x
|
||||
#define DMA_FLOW_LIST 4
|
||||
#define DMA_FLOW_ARRAY 5
|
||||
#define DMA_FLOW_LIST_DEMAND 6
|
||||
#define DMA_FLOW_ARRAY_DEMAND 7
|
||||
#else
|
||||
#define DMA_FLOW_ARRAY 4
|
||||
#define DMA_FLOW_SMALL 6
|
||||
#define DMA_FLOW_LARGE 7
|
||||
#endif
|
||||
|
||||
#define DIMENSION_LINEAR 0
|
||||
#define DIMENSION_2D 1
|
||||
|
|
@ -36,26 +46,80 @@
|
|||
#define DIR_WRITE 1
|
||||
|
||||
#define INTR_DISABLE 0
|
||||
#ifdef CONFIG_BF60x
|
||||
#define INTR_ON_PERI 1
|
||||
#endif
|
||||
#define INTR_ON_BUF 2
|
||||
#define INTR_ON_ROW 3
|
||||
|
||||
#define DMA_NOSYNC_KEEP_DMA_BUF 0
|
||||
#define DMA_SYNC_RESTART 1
|
||||
|
||||
#ifdef DMA_MMR_SIZE_32
|
||||
#define DMA_MMR_SIZE_TYPE long
|
||||
#define DMA_MMR_READ bfin_read32
|
||||
#define DMA_MMR_WRITE bfin_write32
|
||||
#else
|
||||
#define DMA_MMR_SIZE_TYPE short
|
||||
#define DMA_MMR_READ bfin_read16
|
||||
#define DMA_MMR_WRITE bfin_write16
|
||||
#endif
|
||||
|
||||
struct dma_desc_array {
|
||||
unsigned long start_addr;
|
||||
unsigned DMA_MMR_SIZE_TYPE cfg;
|
||||
unsigned DMA_MMR_SIZE_TYPE x_count;
|
||||
DMA_MMR_SIZE_TYPE x_modify;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct dmasg {
|
||||
void *next_desc_addr;
|
||||
unsigned long start_addr;
|
||||
unsigned short cfg;
|
||||
unsigned short x_count;
|
||||
short x_modify;
|
||||
unsigned short y_count;
|
||||
short y_modify;
|
||||
unsigned DMA_MMR_SIZE_TYPE cfg;
|
||||
unsigned DMA_MMR_SIZE_TYPE x_count;
|
||||
DMA_MMR_SIZE_TYPE x_modify;
|
||||
unsigned DMA_MMR_SIZE_TYPE y_count;
|
||||
DMA_MMR_SIZE_TYPE y_modify;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct dma_register {
|
||||
void *next_desc_ptr; /* DMA Next Descriptor Pointer register */
|
||||
unsigned long start_addr; /* DMA Start address register */
|
||||
#ifdef CONFIG_BF60x
|
||||
unsigned long cfg; /* DMA Configuration register */
|
||||
|
||||
unsigned long x_count; /* DMA x_count register */
|
||||
|
||||
long x_modify; /* DMA x_modify register */
|
||||
|
||||
unsigned long y_count; /* DMA y_count register */
|
||||
|
||||
long y_modify; /* DMA y_modify register */
|
||||
|
||||
unsigned long reserved;
|
||||
unsigned long reserved2;
|
||||
|
||||
void *curr_desc_ptr; /* DMA Current Descriptor Pointer
|
||||
register */
|
||||
void *prev_desc_ptr; /* DMA previous initial Descriptor Pointer
|
||||
register */
|
||||
unsigned long curr_addr_ptr; /* DMA Current Address Pointer
|
||||
register */
|
||||
unsigned long irq_status; /* DMA irq status register */
|
||||
|
||||
unsigned long curr_x_count; /* DMA Current x-count register */
|
||||
|
||||
unsigned long curr_y_count; /* DMA Current y-count register */
|
||||
|
||||
unsigned long reserved3;
|
||||
|
||||
unsigned long bw_limit_count; /* DMA band width limit count register */
|
||||
unsigned long curr_bw_limit_count; /* DMA Current band width limit
|
||||
count register */
|
||||
unsigned long bw_monitor_count; /* DMA band width limit count register */
|
||||
unsigned long curr_bw_monitor_count; /* DMA Current band width limit
|
||||
count register */
|
||||
#else
|
||||
unsigned short cfg; /* DMA Configuration register */
|
||||
unsigned short dummy1; /* DMA Configuration register */
|
||||
|
||||
|
|
@ -92,6 +156,7 @@ struct dma_register {
|
|||
unsigned short dummy9;
|
||||
|
||||
unsigned long reserved3;
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
|
|
@ -131,23 +196,23 @@ static inline void set_dma_curr_desc_addr(unsigned int channel, void *addr)
|
|||
{
|
||||
dma_ch[channel].regs->curr_desc_ptr = addr;
|
||||
}
|
||||
static inline void set_dma_x_count(unsigned int channel, unsigned short x_count)
|
||||
static inline void set_dma_x_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE x_count)
|
||||
{
|
||||
dma_ch[channel].regs->x_count = x_count;
|
||||
}
|
||||
static inline void set_dma_y_count(unsigned int channel, unsigned short y_count)
|
||||
static inline void set_dma_y_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE y_count)
|
||||
{
|
||||
dma_ch[channel].regs->y_count = y_count;
|
||||
}
|
||||
static inline void set_dma_x_modify(unsigned int channel, short x_modify)
|
||||
static inline void set_dma_x_modify(unsigned int channel, DMA_MMR_SIZE_TYPE x_modify)
|
||||
{
|
||||
dma_ch[channel].regs->x_modify = x_modify;
|
||||
}
|
||||
static inline void set_dma_y_modify(unsigned int channel, short y_modify)
|
||||
static inline void set_dma_y_modify(unsigned int channel, DMA_MMR_SIZE_TYPE y_modify)
|
||||
{
|
||||
dma_ch[channel].regs->y_modify = y_modify;
|
||||
}
|
||||
static inline void set_dma_config(unsigned int channel, unsigned short config)
|
||||
static inline void set_dma_config(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE config)
|
||||
{
|
||||
dma_ch[channel].regs->cfg = config;
|
||||
}
|
||||
|
|
@ -156,23 +221,55 @@ static inline void set_dma_curr_addr(unsigned int channel, unsigned long addr)
|
|||
dma_ch[channel].regs->curr_addr_ptr = addr;
|
||||
}
|
||||
|
||||
static inline unsigned short
|
||||
set_bfin_dma_config(char direction, char flow_mode,
|
||||
char intr_mode, char dma_mode, char width, char syncmode)
|
||||
#ifdef CONFIG_BF60x
|
||||
static inline unsigned long
|
||||
set_bfin_dma_config2(char direction, char flow_mode, char intr_mode,
|
||||
char dma_mode, char mem_width, char syncmode, char peri_width)
|
||||
{
|
||||
return (direction << 1) | (width << 2) | (dma_mode << 4) |
|
||||
unsigned long config = 0;
|
||||
|
||||
switch (intr_mode) {
|
||||
case INTR_ON_BUF:
|
||||
if (dma_mode == DIMENSION_2D)
|
||||
config = DI_EN_Y;
|
||||
else
|
||||
config = DI_EN_X;
|
||||
break;
|
||||
case INTR_ON_ROW:
|
||||
config = DI_EN_X;
|
||||
break;
|
||||
case INTR_ON_PERI:
|
||||
config = DI_EN_P;
|
||||
break;
|
||||
};
|
||||
|
||||
return config | (direction << 1) | (mem_width << 8) | (dma_mode << 26) |
|
||||
(flow_mode << 12) | (syncmode << 2) | (peri_width << 4);
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline unsigned DMA_MMR_SIZE_TYPE
|
||||
set_bfin_dma_config(char direction, char flow_mode,
|
||||
char intr_mode, char dma_mode, char mem_width, char syncmode)
|
||||
{
|
||||
#ifdef CONFIG_BF60x
|
||||
return set_bfin_dma_config2(direction, flow_mode, intr_mode, dma_mode,
|
||||
mem_width, syncmode, mem_width);
|
||||
#else
|
||||
return (direction << 1) | (mem_width << 2) | (dma_mode << 4) |
|
||||
(intr_mode << 6) | (flow_mode << 12) | (syncmode << 5);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline unsigned short get_dma_curr_irqstat(unsigned int channel)
|
||||
static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_irqstat(unsigned int channel)
|
||||
{
|
||||
return dma_ch[channel].regs->irq_status;
|
||||
}
|
||||
static inline unsigned short get_dma_curr_xcount(unsigned int channel)
|
||||
static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_xcount(unsigned int channel)
|
||||
{
|
||||
return dma_ch[channel].regs->curr_x_count;
|
||||
}
|
||||
static inline unsigned short get_dma_curr_ycount(unsigned int channel)
|
||||
static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_ycount(unsigned int channel)
|
||||
{
|
||||
return dma_ch[channel].regs->curr_y_count;
|
||||
}
|
||||
|
|
@ -184,7 +281,7 @@ static inline void *get_dma_curr_desc_ptr(unsigned int channel)
|
|||
{
|
||||
return dma_ch[channel].regs->curr_desc_ptr;
|
||||
}
|
||||
static inline unsigned short get_dma_config(unsigned int channel)
|
||||
static inline unsigned DMA_MMR_SIZE_TYPE get_dma_config(unsigned int channel)
|
||||
{
|
||||
return dma_ch[channel].regs->cfg;
|
||||
}
|
||||
|
|
@ -203,8 +300,8 @@ static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize
|
|||
|
||||
dma_ch[channel].regs->next_desc_ptr = sg;
|
||||
dma_ch[channel].regs->cfg =
|
||||
(dma_ch[channel].regs->cfg & ~(0xf << 8)) |
|
||||
((ndsize & 0xf) << 8);
|
||||
(dma_ch[channel].regs->cfg & ~NDSIZE) |
|
||||
((ndsize << NDSIZE_OFFSET) & NDSIZE);
|
||||
}
|
||||
|
||||
static inline int dma_channel_active(unsigned int channel)
|
||||
|
|
@ -239,7 +336,7 @@ static inline void dma_enable_irq(unsigned int channel)
|
|||
}
|
||||
static inline void clear_dma_irqstat(unsigned int channel)
|
||||
{
|
||||
dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR;
|
||||
dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR | DMA_PIRQ;
|
||||
}
|
||||
|
||||
void *dma_memcpy(void *dest, const void *src, size_t count);
|
||||
|
|
|
|||
|
|
@ -29,24 +29,28 @@ extern void sigreturn_stub(void);
|
|||
#endif
|
||||
#endif
|
||||
|
||||
#define FIXED_CODE_START 0x400
|
||||
#ifndef CONFIG_PHY_RAM_BASE_ADDRESS
|
||||
#define CONFIG_PHY_RAM_BASE_ADDRESS 0x0
|
||||
#endif
|
||||
|
||||
#define SIGRETURN_STUB 0x400
|
||||
#define FIXED_CODE_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400)
|
||||
|
||||
#define ATOMIC_SEQS_START 0x410
|
||||
#define SIGRETURN_STUB (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400)
|
||||
|
||||
#define ATOMIC_XCHG32 0x410
|
||||
#define ATOMIC_CAS32 0x420
|
||||
#define ATOMIC_ADD32 0x430
|
||||
#define ATOMIC_SUB32 0x440
|
||||
#define ATOMIC_IOR32 0x450
|
||||
#define ATOMIC_AND32 0x460
|
||||
#define ATOMIC_XOR32 0x470
|
||||
#define ATOMIC_SEQS_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410)
|
||||
|
||||
#define ATOMIC_SEQS_END 0x480
|
||||
#define ATOMIC_XCHG32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410)
|
||||
#define ATOMIC_CAS32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x420)
|
||||
#define ATOMIC_ADD32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x430)
|
||||
#define ATOMIC_SUB32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x440)
|
||||
#define ATOMIC_IOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x450)
|
||||
#define ATOMIC_AND32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x460)
|
||||
#define ATOMIC_XOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x470)
|
||||
|
||||
#define SAFE_USER_INSTRUCTION 0x480
|
||||
#define ATOMIC_SEQS_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480)
|
||||
|
||||
#define FIXED_CODE_END 0x490
|
||||
#define SAFE_USER_INSTRUCTION (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480)
|
||||
|
||||
#define FIXED_CODE_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x490)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -7,14 +7,15 @@
|
|||
#ifndef _BLACKFIN_PAGE_H
|
||||
#define _BLACKFIN_PAGE_H
|
||||
|
||||
#include <asm-generic/page.h>
|
||||
#define MAP_NR(addr) (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)
|
||||
#define ARCH_PFN_OFFSET (CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT)
|
||||
#define MAP_NR(addr) ((unsigned long)(addr) >> PAGE_SHIFT)
|
||||
|
||||
#define VM_DATA_DEFAULT_FLAGS \
|
||||
(VM_READ | VM_WRITE | \
|
||||
((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0 ) | \
|
||||
VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
|
||||
|
||||
#include <asm-generic/page.h>
|
||||
#include <asm-generic/memory_model.h>
|
||||
#include <asm-generic/getorder.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -45,9 +45,15 @@ static int __init blackfin_dma_init(void)
|
|||
atomic_set(&dma_ch[i].chan_status, 0);
|
||||
dma_ch[i].regs = dma_io_base_addr[i];
|
||||
}
|
||||
#ifdef CH_MEM_STREAM3_SRC
|
||||
/* Mark MEMDMA Channel 3 as requested since we're using it internally */
|
||||
request_dma(CH_MEM_STREAM3_DEST, "Blackfin dma_memcpy");
|
||||
request_dma(CH_MEM_STREAM3_SRC, "Blackfin dma_memcpy");
|
||||
#else
|
||||
/* Mark MEMDMA Channel 0 as requested since we're using it internally */
|
||||
request_dma(CH_MEM_STREAM0_DEST, "Blackfin dma_memcpy");
|
||||
request_dma(CH_MEM_STREAM0_SRC, "Blackfin dma_memcpy");
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_DEB_DMA_URGENT)
|
||||
bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE()
|
||||
|
|
@ -204,6 +210,7 @@ EXPORT_SYMBOL(free_dma);
|
|||
# ifndef MAX_DMA_SUSPEND_CHANNELS
|
||||
# define MAX_DMA_SUSPEND_CHANNELS MAX_DMA_CHANNELS
|
||||
# endif
|
||||
# ifndef CONFIG_BF60x
|
||||
int blackfin_dma_suspend(void)
|
||||
{
|
||||
int i;
|
||||
|
|
@ -213,7 +220,6 @@ int blackfin_dma_suspend(void)
|
|||
printk(KERN_ERR "DMA Channel %d failed to suspend\n", i);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
if (i < MAX_DMA_SUSPEND_CHANNELS)
|
||||
dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map;
|
||||
}
|
||||
|
|
@ -230,7 +236,6 @@ void blackfin_dma_resume(void)
|
|||
|
||||
for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
|
||||
dma_ch[i].regs->cfg = 0;
|
||||
|
||||
if (i < MAX_DMA_SUSPEND_CHANNELS)
|
||||
dma_ch[i].regs->peripheral_map = dma_ch[i].saved_peripheral_map;
|
||||
}
|
||||
|
|
@ -238,6 +243,16 @@ void blackfin_dma_resume(void)
|
|||
bfin_write_DMAC_TC_PER(0x0111);
|
||||
#endif
|
||||
}
|
||||
# else
|
||||
int blackfin_dma_suspend(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
void blackfin_dma_resume(void)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
|
@ -279,10 +294,10 @@ void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size)
|
|||
src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR;
|
||||
}
|
||||
|
||||
if (!bfin_read16(&src_ch->cfg))
|
||||
if (!DMA_MMR_READ(&src_ch->cfg))
|
||||
break;
|
||||
else if (bfin_read16(&dst_ch->irq_status) & DMA_DONE) {
|
||||
bfin_write16(&src_ch->cfg, 0);
|
||||
else if (DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE) {
|
||||
DMA_MMR_WRITE(&src_ch->cfg, 0);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -295,22 +310,31 @@ void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size)
|
|||
|
||||
/* Destination */
|
||||
bfin_write32(&dst_ch->start_addr, dst);
|
||||
bfin_write16(&dst_ch->x_count, size >> 2);
|
||||
bfin_write16(&dst_ch->x_modify, 1 << 2);
|
||||
bfin_write16(&dst_ch->irq_status, DMA_DONE | DMA_ERR);
|
||||
DMA_MMR_WRITE(&dst_ch->x_count, size >> 2);
|
||||
DMA_MMR_WRITE(&dst_ch->x_modify, 1 << 2);
|
||||
DMA_MMR_WRITE(&dst_ch->irq_status, DMA_DONE | DMA_ERR);
|
||||
|
||||
/* Source */
|
||||
bfin_write32(&src_ch->start_addr, src);
|
||||
bfin_write16(&src_ch->x_count, size >> 2);
|
||||
bfin_write16(&src_ch->x_modify, 1 << 2);
|
||||
bfin_write16(&src_ch->irq_status, DMA_DONE | DMA_ERR);
|
||||
DMA_MMR_WRITE(&src_ch->x_count, size >> 2);
|
||||
DMA_MMR_WRITE(&src_ch->x_modify, 1 << 2);
|
||||
DMA_MMR_WRITE(&src_ch->irq_status, DMA_DONE | DMA_ERR);
|
||||
|
||||
/* Enable */
|
||||
bfin_write16(&src_ch->cfg, DMAEN | WDSIZE_32);
|
||||
bfin_write16(&dst_ch->cfg, WNR | DI_EN | DMAEN | WDSIZE_32);
|
||||
DMA_MMR_WRITE(&src_ch->cfg, DMAEN | WDSIZE_32);
|
||||
DMA_MMR_WRITE(&dst_ch->cfg, WNR | DI_EN_X | DMAEN | WDSIZE_32);
|
||||
|
||||
/* Since we are atomic now, don't use the workaround ssync */
|
||||
__builtin_bfin_ssync();
|
||||
|
||||
#ifdef CONFIG_BF60x
|
||||
/* Work around a possible MDMA anomaly. Running 2 MDMA channels to
|
||||
* transfer DDR data to L1 SRAM may corrupt data.
|
||||
* Should be reverted after this issue is root caused.
|
||||
*/
|
||||
while (!(DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE))
|
||||
continue;
|
||||
#endif
|
||||
}
|
||||
|
||||
void __init early_dma_memcpy_done(void)
|
||||
|
|
@ -336,6 +360,42 @@ void __init early_dma_memcpy_done(void)
|
|||
__builtin_bfin_ssync();
|
||||
}
|
||||
|
||||
#ifdef CH_MEM_STREAM3_SRC
|
||||
#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S3_CONFIG
|
||||
#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S3_CONFIG
|
||||
#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S3_START_ADDR
|
||||
#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S3_IRQ_STATUS
|
||||
#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S3_X_COUNT
|
||||
#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S3_X_MODIFY
|
||||
#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S3_Y_COUNT
|
||||
#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S3_Y_MODIFY
|
||||
#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D3_CONFIG
|
||||
#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D3_START_ADDR
|
||||
#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D3_IRQ_STATUS
|
||||
#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D3_IRQ_STATUS
|
||||
#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D3_X_COUNT
|
||||
#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D3_X_MODIFY
|
||||
#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D3_Y_COUNT
|
||||
#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D3_Y_MODIFY
|
||||
#else
|
||||
#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S0_CONFIG
|
||||
#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S0_CONFIG
|
||||
#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S0_START_ADDR
|
||||
#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S0_IRQ_STATUS
|
||||
#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S0_X_COUNT
|
||||
#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S0_X_MODIFY
|
||||
#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S0_Y_COUNT
|
||||
#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S0_Y_MODIFY
|
||||
#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D0_CONFIG
|
||||
#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D0_START_ADDR
|
||||
#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D0_IRQ_STATUS
|
||||
#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D0_IRQ_STATUS
|
||||
#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D0_X_COUNT
|
||||
#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D0_X_MODIFY
|
||||
#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D0_Y_COUNT
|
||||
#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D0_Y_MODIFY
|
||||
#endif
|
||||
|
||||
/**
|
||||
* __dma_memcpy - program the MDMA registers
|
||||
*
|
||||
|
|
@ -358,8 +418,8 @@ static void __dma_memcpy(u32 daddr, s16 dmod, u32 saddr, s16 smod, size_t cnt, u
|
|||
*/
|
||||
__builtin_bfin_ssync();
|
||||
|
||||
if (bfin_read_MDMA_S0_CONFIG())
|
||||
while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE))
|
||||
if (bfin_read_MDMA_S_CONFIG())
|
||||
while (!(bfin_read_MDMA_D_IRQ_STATUS() & DMA_DONE))
|
||||
continue;
|
||||
|
||||
if (conf & DMA2D) {
|
||||
|
|
@ -374,39 +434,42 @@ static void __dma_memcpy(u32 daddr, s16 dmod, u32 saddr, s16 smod, size_t cnt, u
|
|||
u32 shift = abs(dmod) >> 1;
|
||||
size_t ycnt = cnt >> (16 - shift);
|
||||
cnt = 1 << (16 - shift);
|
||||
bfin_write_MDMA_D0_Y_COUNT(ycnt);
|
||||
bfin_write_MDMA_S0_Y_COUNT(ycnt);
|
||||
bfin_write_MDMA_D0_Y_MODIFY(dmod);
|
||||
bfin_write_MDMA_S0_Y_MODIFY(smod);
|
||||
bfin_write_MDMA_D_Y_COUNT(ycnt);
|
||||
bfin_write_MDMA_S_Y_COUNT(ycnt);
|
||||
bfin_write_MDMA_D_Y_MODIFY(dmod);
|
||||
bfin_write_MDMA_S_Y_MODIFY(smod);
|
||||
}
|
||||
|
||||
bfin_write_MDMA_D0_START_ADDR(daddr);
|
||||
bfin_write_MDMA_D0_X_COUNT(cnt);
|
||||
bfin_write_MDMA_D0_X_MODIFY(dmod);
|
||||
bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
||||
bfin_write_MDMA_D_START_ADDR(daddr);
|
||||
bfin_write_MDMA_D_X_COUNT(cnt);
|
||||
bfin_write_MDMA_D_X_MODIFY(dmod);
|
||||
bfin_write_MDMA_D_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
||||
|
||||
bfin_write_MDMA_S0_START_ADDR(saddr);
|
||||
bfin_write_MDMA_S0_X_COUNT(cnt);
|
||||
bfin_write_MDMA_S0_X_MODIFY(smod);
|
||||
bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
||||
bfin_write_MDMA_S_START_ADDR(saddr);
|
||||
bfin_write_MDMA_S_X_COUNT(cnt);
|
||||
bfin_write_MDMA_S_X_MODIFY(smod);
|
||||
bfin_write_MDMA_S_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
||||
|
||||
bfin_write_MDMA_S0_CONFIG(DMAEN | conf);
|
||||
bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | conf);
|
||||
bfin_write_MDMA_S_CONFIG(DMAEN | conf);
|
||||
if (conf & DMA2D)
|
||||
bfin_write_MDMA_D_CONFIG(WNR | DI_EN_Y | DMAEN | conf);
|
||||
else
|
||||
bfin_write_MDMA_D_CONFIG(WNR | DI_EN_X | DMAEN | conf);
|
||||
|
||||
spin_unlock_irqrestore(&mdma_lock, flags);
|
||||
|
||||
SSYNC();
|
||||
|
||||
while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE))
|
||||
if (bfin_read_MDMA_S0_CONFIG())
|
||||
while (!(bfin_read_MDMA_D_IRQ_STATUS() & DMA_DONE))
|
||||
if (bfin_read_MDMA_S_CONFIG())
|
||||
continue;
|
||||
else
|
||||
return;
|
||||
|
||||
bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
||||
bfin_write_MDMA_D_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
||||
|
||||
bfin_write_MDMA_S0_CONFIG(0);
|
||||
bfin_write_MDMA_D0_CONFIG(0);
|
||||
bfin_write_MDMA_S_CONFIG(0);
|
||||
bfin_write_MDMA_D_CONFIG(0);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -448,8 +511,10 @@ static void *_dma_memcpy(void *pdst, const void *psrc, size_t size)
|
|||
}
|
||||
size >>= shift;
|
||||
|
||||
#ifndef DMA_MMR_SIZE_32
|
||||
if (size > 0x10000)
|
||||
conf |= DMA2D;
|
||||
#endif
|
||||
|
||||
__dma_memcpy(dst, mod, src, mod, size, conf);
|
||||
|
||||
|
|
@ -488,6 +553,9 @@ EXPORT_SYMBOL(dma_memcpy);
|
|||
*/
|
||||
void *dma_memcpy_nocache(void *pdst, const void *psrc, size_t size)
|
||||
{
|
||||
#ifdef DMA_MMR_SIZE_32
|
||||
_dma_memcpy(pdst, psrc, size);
|
||||
#else
|
||||
size_t bulk, rest;
|
||||
|
||||
bulk = size & ~0xffff;
|
||||
|
|
@ -495,6 +563,7 @@ void *dma_memcpy_nocache(void *pdst, const void *psrc, size_t size)
|
|||
if (bulk)
|
||||
_dma_memcpy(pdst, psrc, bulk);
|
||||
_dma_memcpy(pdst + bulk, psrc + bulk, rest);
|
||||
#endif
|
||||
return pdst;
|
||||
}
|
||||
EXPORT_SYMBOL(dma_memcpy_nocache);
|
||||
|
|
@ -514,14 +583,14 @@ void *safe_dma_memcpy(void *dst, const void *src, size_t size)
|
|||
}
|
||||
EXPORT_SYMBOL(safe_dma_memcpy);
|
||||
|
||||
static void _dma_out(unsigned long addr, unsigned long buf, unsigned short len,
|
||||
static void _dma_out(unsigned long addr, unsigned long buf, unsigned DMA_MMR_SIZE_TYPE len,
|
||||
u16 size, u16 dma_size)
|
||||
{
|
||||
blackfin_dcache_flush_range(buf, buf + len * size);
|
||||
__dma_memcpy(addr, 0, buf, size, len, dma_size);
|
||||
}
|
||||
|
||||
static void _dma_in(unsigned long addr, unsigned long buf, unsigned short len,
|
||||
static void _dma_in(unsigned long addr, unsigned long buf, unsigned DMA_MMR_SIZE_TYPE len,
|
||||
u16 size, u16 dma_size)
|
||||
{
|
||||
blackfin_dcache_invalidate_range(buf, buf + len * size);
|
||||
|
|
@ -529,7 +598,7 @@ static void _dma_in(unsigned long addr, unsigned long buf, unsigned short len,
|
|||
}
|
||||
|
||||
#define MAKE_DMA_IO(io, bwl, isize, dmasize, cnst) \
|
||||
void dma_##io##s##bwl(unsigned long addr, cnst void *buf, unsigned short len) \
|
||||
void dma_##io##s##bwl(unsigned long addr, cnst void *buf, unsigned DMA_MMR_SIZE_TYPE len) \
|
||||
{ \
|
||||
_dma_##io(addr, (unsigned long)buf, len, isize, WDSIZE_##dmasize); \
|
||||
} \
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@ static struct gpio_port_t * const gpio_array[] = {
|
|||
(struct gpio_port_t *) FIO0_FLAG_D,
|
||||
(struct gpio_port_t *) FIO1_FLAG_D,
|
||||
(struct gpio_port_t *) FIO2_FLAG_D,
|
||||
#elif defined(CONFIG_BF54x)
|
||||
#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
|
||||
(struct gpio_port_t *)PORTA_FER,
|
||||
(struct gpio_port_t *)PORTB_FER,
|
||||
(struct gpio_port_t *)PORTC_FER,
|
||||
|
|
@ -66,6 +66,7 @@ static struct gpio_port_t * const gpio_array[] = {
|
|||
(struct gpio_port_t *)PORTE_FER,
|
||||
(struct gpio_port_t *)PORTF_FER,
|
||||
(struct gpio_port_t *)PORTG_FER,
|
||||
#elif defined(CONFIG_BF54x)
|
||||
(struct gpio_port_t *)PORTH_FER,
|
||||
(struct gpio_port_t *)PORTI_FER,
|
||||
(struct gpio_port_t *)PORTJ_FER,
|
||||
|
|
@ -210,7 +211,7 @@ static void port_setup(unsigned gpio, unsigned short usage)
|
|||
else
|
||||
*port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
|
||||
SSYNC();
|
||||
#elif defined(CONFIG_BF54x)
|
||||
#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
|
||||
if (usage == GPIO_USAGE)
|
||||
gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
|
||||
else
|
||||
|
|
@ -299,7 +300,7 @@ static void portmux_setup(unsigned short per)
|
|||
pmux |= (function << offset);
|
||||
bfin_write_PORT_MUX(pmux);
|
||||
}
|
||||
#elif defined(CONFIG_BF54x)
|
||||
#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
|
||||
inline void portmux_setup(unsigned short per)
|
||||
{
|
||||
u16 ident = P_IDENT(per);
|
||||
|
|
@ -377,7 +378,7 @@ static int portmux_group_check(unsigned short per)
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_BF54x
|
||||
#if !(defined(CONFIG_BF54x) || defined(CONFIG_BF60x))
|
||||
/***********************************************************
|
||||
*
|
||||
* FUNCTIONS: Blackfin General Purpose Ports Access Functions
|
||||
|
|
@ -680,7 +681,7 @@ void bfin_gpio_pm_hibernate_restore(void)
|
|||
|
||||
|
||||
#endif
|
||||
#else /* CONFIG_BF54x */
|
||||
#else /* CONFIG_BF54x || CONFIG_BF60x */
|
||||
#ifdef CONFIG_PM
|
||||
|
||||
int bfin_pm_standby_ctrl(unsigned ctrl)
|
||||
|
|
@ -726,7 +727,7 @@ unsigned short get_gpio_dir(unsigned gpio)
|
|||
}
|
||||
EXPORT_SYMBOL(get_gpio_dir);
|
||||
|
||||
#endif /* CONFIG_BF54x */
|
||||
#endif /* CONFIG_BF54x || CONFIG_BF60x */
|
||||
|
||||
/***********************************************************
|
||||
*
|
||||
|
|
@ -783,7 +784,7 @@ int peripheral_request(unsigned short per, const char *label)
|
|||
* be requested and used by several drivers
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_BF54x
|
||||
#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
|
||||
if (!((per & P_MAYSHARE) && get_portmux(per) == P_FUNCT2MUX(per))) {
|
||||
#else
|
||||
if (!(per & P_MAYSHARE)) {
|
||||
|
|
@ -937,7 +938,7 @@ int bfin_gpio_request(unsigned gpio, const char *label)
|
|||
printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!"
|
||||
" (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio);
|
||||
}
|
||||
#ifndef CONFIG_BF54x
|
||||
#if !(defined(CONFIG_BF54x) || defined(CONFIG_BF60x))
|
||||
else { /* Reset POLAR setting when acquiring a gpio for the first time */
|
||||
set_gpio_polar(gpio, 0);
|
||||
}
|
||||
|
|
@ -1110,7 +1111,7 @@ void bfin_gpio_irq_free(unsigned gpio)
|
|||
|
||||
static inline void __bfin_gpio_direction_input(unsigned gpio)
|
||||
{
|
||||
#ifdef CONFIG_BF54x
|
||||
#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
|
||||
gpio_array[gpio_bank(gpio)]->dir_clear = gpio_bit(gpio);
|
||||
#else
|
||||
gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
|
||||
|
|
@ -1138,13 +1139,13 @@ EXPORT_SYMBOL(bfin_gpio_direction_input);
|
|||
|
||||
void bfin_gpio_irq_prepare(unsigned gpio)
|
||||
{
|
||||
#ifdef CONFIG_BF54x
|
||||
#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
|
||||
unsigned long flags;
|
||||
#endif
|
||||
|
||||
port_setup(gpio, GPIO_USAGE);
|
||||
|
||||
#ifdef CONFIG_BF54x
|
||||
#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
|
||||
flags = hard_local_irq_save();
|
||||
__bfin_gpio_direction_input(gpio);
|
||||
hard_local_irq_restore(flags);
|
||||
|
|
@ -1173,7 +1174,7 @@ int bfin_gpio_direction_output(unsigned gpio, int value)
|
|||
|
||||
gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
|
||||
gpio_set_value(gpio, value);
|
||||
#ifdef CONFIG_BF54x
|
||||
#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
|
||||
gpio_array[gpio_bank(gpio)]->dir_set = gpio_bit(gpio);
|
||||
#else
|
||||
gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
|
||||
|
|
@ -1188,7 +1189,7 @@ EXPORT_SYMBOL(bfin_gpio_direction_output);
|
|||
|
||||
int bfin_gpio_get_value(unsigned gpio)
|
||||
{
|
||||
#ifdef CONFIG_BF54x
|
||||
#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
|
||||
return (1 & (gpio_array[gpio_bank(gpio)]->data >> gpio_sub_n(gpio)));
|
||||
#else
|
||||
unsigned long flags;
|
||||
|
|
|
|||
|
|
@ -105,6 +105,7 @@ DEFINE_SYSREG(seqstat, , );
|
|||
DEFINE_SYSREG(syscfg, , CSYNC());
|
||||
#define D_SYSREG(sr) debugfs_create_file(#sr, S_IRUSR|S_IWUSR, parent, NULL, &fops_sysreg_##sr)
|
||||
|
||||
#ifndef CONFIG_BF60x
|
||||
/*
|
||||
* CAN
|
||||
*/
|
||||
|
|
@ -223,8 +224,10 @@ bfin_debug_mmrs_dma(struct dentry *parent, unsigned long base, int num, char mdm
|
|||
__DMA(CURR_DESC_PTR, curr_desc_ptr);
|
||||
__DMA(CURR_ADDR, curr_addr);
|
||||
__DMA(IRQ_STATUS, irq_status);
|
||||
#ifndef CONFIG_BF60x
|
||||
if (strcmp(pfx, "IMDMA") != 0)
|
||||
__DMA(PERIPHERAL_MAP, peripheral_map);
|
||||
#endif
|
||||
__DMA(CURR_X_COUNT, curr_x_count);
|
||||
__DMA(CURR_Y_COUNT, curr_y_count);
|
||||
}
|
||||
|
|
@ -568,7 +571,7 @@ bfin_debug_mmrs_uart(struct dentry *parent, unsigned long base, int num)
|
|||
#endif
|
||||
}
|
||||
#define UART(num) bfin_debug_mmrs_uart(parent, UART##num##_DLL, num)
|
||||
|
||||
#endif /* CONFIG_BF60x */
|
||||
/*
|
||||
* The actual debugfs generation
|
||||
*/
|
||||
|
|
@ -740,7 +743,7 @@ static int __init bfin_debug_mmrs_init(void)
|
|||
D32(WPDACNT0);
|
||||
D32(WPDACNT1);
|
||||
D32(WPSTAT);
|
||||
|
||||
#ifndef CONFIG_BF60x
|
||||
/* System MMRs */
|
||||
#ifdef ATAPI_CONTROL
|
||||
parent = debugfs_create_dir("atapi", top);
|
||||
|
|
@ -1873,7 +1876,7 @@ static int __init bfin_debug_mmrs_init(void)
|
|||
|
||||
}
|
||||
#endif /* BF54x */
|
||||
|
||||
#endif /* CONFIG_BF60x */
|
||||
debug_mmrs_dentry = top;
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -95,7 +95,9 @@ void cpu_idle(void)
|
|||
idle();
|
||||
rcu_idle_exit();
|
||||
tick_nohz_idle_exit();
|
||||
schedule_preempt_disabled();
|
||||
preempt_enable_no_resched();
|
||||
schedule();
|
||||
preempt_disable();
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -329,12 +331,16 @@ int in_mem_const(unsigned long addr, unsigned long size,
|
|||
{
|
||||
return in_mem_const_off(addr, size, 0, const_addr, const_size);
|
||||
}
|
||||
#ifdef CONFIG_BF60x
|
||||
#define ASYNC_ENABLED(bnum, bctlnum) 1
|
||||
#else
|
||||
#define ASYNC_ENABLED(bnum, bctlnum) \
|
||||
({ \
|
||||
(bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \
|
||||
bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \
|
||||
1; \
|
||||
})
|
||||
#endif
|
||||
/*
|
||||
* We can't read EBIU banks that aren't enabled or we end up hanging
|
||||
* on the access to the async space. Make sure we validate accesses
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
__attribute__ ((__l1_text__, __noreturn__))
|
||||
static void bfin_reset(void)
|
||||
{
|
||||
#ifndef CONFIG_BF60x
|
||||
if (!ANOMALY_05000353 && !ANOMALY_05000386)
|
||||
bfrom_SoftReset((void *)(L1_SCRATCH_START + L1_SCRATCH_LENGTH - 20));
|
||||
|
||||
|
|
@ -57,7 +58,6 @@ static void bfin_reset(void)
|
|||
if (__SILICON_REVISION__ < 1 && bfin_revid() < 1)
|
||||
bfin_read_SWRST();
|
||||
#endif
|
||||
|
||||
/* Wait for the SWRST write to complete. Cannot rely on SSYNC
|
||||
* though as the System state is all reset now.
|
||||
*/
|
||||
|
|
@ -72,6 +72,10 @@ static void bfin_reset(void)
|
|||
while (1)
|
||||
/* Issue core reset */
|
||||
asm("raise 1");
|
||||
#else
|
||||
while (1)
|
||||
bfin_write_RCU0_CTL(0x1);
|
||||
#endif
|
||||
}
|
||||
|
||||
__attribute__((weak))
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@
|
|||
#include <asm/cacheflush.h>
|
||||
#include <asm/blackfin.h>
|
||||
#include <asm/cplbinit.h>
|
||||
#include <asm/clocks.h>
|
||||
#include <asm/div64.h>
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/fixed_code.h>
|
||||
|
|
@ -550,7 +551,6 @@ static __init void memory_setup(void)
|
|||
{
|
||||
#ifdef CONFIG_MTD_UCLINUX
|
||||
unsigned long mtd_phys = 0;
|
||||
unsigned long n;
|
||||
#endif
|
||||
unsigned long max_mem;
|
||||
|
||||
|
|
@ -594,9 +594,9 @@ static __init void memory_setup(void)
|
|||
mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8)));
|
||||
|
||||
# if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS)
|
||||
n = ext2_image_size((void *)(mtd_phys + 0x400));
|
||||
if (n)
|
||||
mtd_size = PAGE_ALIGN(n * 1024);
|
||||
if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC)
|
||||
mtd_size =
|
||||
PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10);
|
||||
# endif
|
||||
|
||||
# if defined(CONFIG_CRAMFS)
|
||||
|
|
@ -612,7 +612,8 @@ static __init void memory_setup(void)
|
|||
|
||||
/* ROM_FS is XIP, so if we found it, we need to limit memory */
|
||||
if (memory_end > max_mem) {
|
||||
pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", max_mem >> 20);
|
||||
pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n",
|
||||
(max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
|
||||
memory_end = max_mem;
|
||||
}
|
||||
}
|
||||
|
|
@ -642,7 +643,8 @@ static __init void memory_setup(void)
|
|||
* doesn't exist, or we don't need to - then dont.
|
||||
*/
|
||||
if (memory_end > max_mem) {
|
||||
pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", max_mem >> 20);
|
||||
pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n",
|
||||
(max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
|
||||
memory_end = max_mem;
|
||||
}
|
||||
|
||||
|
|
@ -661,8 +663,8 @@ static __init void memory_setup(void)
|
|||
init_mm.end_data = (unsigned long)_edata;
|
||||
init_mm.brk = (unsigned long)0;
|
||||
|
||||
printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20);
|
||||
printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20);
|
||||
printk(KERN_INFO "Board Memory: %ldMB\n", (physical_mem_end - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
|
||||
printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", (_ramend - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
|
||||
|
||||
printk(KERN_INFO "Memory map:\n"
|
||||
" fixedcode = 0x%p-0x%p\n"
|
||||
|
|
@ -705,7 +707,7 @@ void __init find_min_max_pfn(void)
|
|||
int i;
|
||||
|
||||
max_pfn = 0;
|
||||
min_low_pfn = memory_end;
|
||||
min_low_pfn = PFN_DOWN(memory_end);
|
||||
|
||||
for (i = 0; i < bfin_memmap.nr_map; i++) {
|
||||
unsigned long start, end;
|
||||
|
|
@ -748,8 +750,7 @@ static __init void setup_bootmem_allocator(void)
|
|||
/* pfn of the first usable page frame after kernel image*/
|
||||
if (min_low_pfn < memory_start >> PAGE_SHIFT)
|
||||
min_low_pfn = memory_start >> PAGE_SHIFT;
|
||||
|
||||
start_pfn = PAGE_OFFSET >> PAGE_SHIFT;
|
||||
start_pfn = CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT;
|
||||
end_pfn = memory_end >> PAGE_SHIFT;
|
||||
|
||||
/*
|
||||
|
|
@ -794,8 +795,8 @@ static __init void setup_bootmem_allocator(void)
|
|||
}
|
||||
|
||||
/* reserve memory before memory_start, including bootmap */
|
||||
reserve_bootmem(PAGE_OFFSET,
|
||||
memory_start + bootmap_size + PAGE_SIZE - 1 - PAGE_OFFSET,
|
||||
reserve_bootmem(CONFIG_PHY_RAM_BASE_ADDRESS,
|
||||
memory_start + bootmap_size + PAGE_SIZE - 1 - CONFIG_PHY_RAM_BASE_ADDRESS,
|
||||
BOOTMEM_DEFAULT);
|
||||
}
|
||||
|
||||
|
|
@ -844,13 +845,40 @@ static inline int __init get_mem_size(void)
|
|||
break;
|
||||
}
|
||||
switch (ddrctl & 0x30000) {
|
||||
case DEVWD_4: ret *= 2;
|
||||
case DEVWD_8: ret *= 2;
|
||||
case DEVWD_16: break;
|
||||
case DEVWD_4:
|
||||
ret *= 2;
|
||||
case DEVWD_8:
|
||||
ret *= 2;
|
||||
case DEVWD_16:
|
||||
break;
|
||||
}
|
||||
if ((ddrctl & 0xc000) == 0x4000)
|
||||
ret *= 2;
|
||||
return ret;
|
||||
#elif defined(CONFIG_BF60x)
|
||||
u32 ddrctl = bfin_read_DDR0_CFG();
|
||||
int ret;
|
||||
switch (ddrctl & 0xf00) {
|
||||
case DEVSZ_64:
|
||||
ret = 64 / 8;
|
||||
break;
|
||||
case DEVSZ_128:
|
||||
ret = 128 / 8;
|
||||
break;
|
||||
case DEVSZ_256:
|
||||
ret = 256 / 8;
|
||||
break;
|
||||
case DEVSZ_512:
|
||||
ret = 512 / 8;
|
||||
break;
|
||||
case DEVSZ_1G:
|
||||
ret = 1024 / 8;
|
||||
break;
|
||||
case DEVSZ_2G:
|
||||
ret = 2048 / 8;
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
#endif
|
||||
BUG();
|
||||
}
|
||||
|
|
@ -864,12 +892,14 @@ void __init setup_arch(char **cmdline_p)
|
|||
{
|
||||
u32 mmr;
|
||||
unsigned long sclk, cclk;
|
||||
struct clk *clk;
|
||||
|
||||
native_machine_early_platform_add_devices();
|
||||
|
||||
enable_shadow_console();
|
||||
|
||||
/* Check to make sure we are running on the right processor */
|
||||
mmr = bfin_cpuid();
|
||||
if (unlikely(CPUID != bfin_cpuid()))
|
||||
printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n",
|
||||
CPU, bfin_cpuid(), bfin_revid());
|
||||
|
|
@ -890,6 +920,10 @@ void __init setup_arch(char **cmdline_p)
|
|||
|
||||
memset(&bfin_memmap, 0, sizeof(bfin_memmap));
|
||||
|
||||
#ifdef CONFIG_BF60x
|
||||
/* Should init clock device before parse command early */
|
||||
clk_init();
|
||||
#endif
|
||||
/* If the user does not specify things on the command line, use
|
||||
* what the bootloader set things up as
|
||||
*/
|
||||
|
|
@ -904,6 +938,7 @@ void __init setup_arch(char **cmdline_p)
|
|||
|
||||
memory_setup();
|
||||
|
||||
#ifndef CONFIG_BF60x
|
||||
/* Initialize Async memory banks */
|
||||
bfin_write_EBIU_AMBCTL0(AMBCTL0VAL);
|
||||
bfin_write_EBIU_AMBCTL1(AMBCTL1VAL);
|
||||
|
|
@ -913,6 +948,7 @@ void __init setup_arch(char **cmdline_p)
|
|||
bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL);
|
||||
bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL);
|
||||
#endif
|
||||
#endif
|
||||
#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
|
||||
bfin_write_PORTF_HYSTERESIS(HYST_PORTF_0_15);
|
||||
bfin_write_PORTG_HYSTERESIS(HYST_PORTG_0_15);
|
||||
|
|
@ -921,8 +957,24 @@ void __init setup_arch(char **cmdline_p)
|
|||
~HYST_NONEGPIO_MASK) | HYST_NONEGPIO);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BF60x
|
||||
clk = clk_get(NULL, "CCLK");
|
||||
if (!IS_ERR(clk)) {
|
||||
cclk = clk_get_rate(clk);
|
||||
clk_put(clk);
|
||||
} else
|
||||
cclk = 0;
|
||||
|
||||
clk = clk_get(NULL, "SCLK0");
|
||||
if (!IS_ERR(clk)) {
|
||||
sclk = clk_get_rate(clk);
|
||||
clk_put(clk);
|
||||
} else
|
||||
sclk = 0;
|
||||
#else
|
||||
cclk = get_cclk();
|
||||
sclk = get_sclk();
|
||||
#endif
|
||||
|
||||
if ((ANOMALY_05000273 || ANOMALY_05000274) && (cclk >> 1) < sclk)
|
||||
panic("ANOMALY 05000273 or 05000274: CCLK must be >= 2*SCLK");
|
||||
|
|
@ -938,7 +990,7 @@ void __init setup_arch(char **cmdline_p)
|
|||
printk(KERN_INFO "Hardware Trace %s and %sabled\n",
|
||||
(mmr & 0x1) ? "active" : "off",
|
||||
(mmr & 0x2) ? "en" : "dis");
|
||||
|
||||
#ifndef CONFIG_BF60x
|
||||
mmr = bfin_read_SYSCR();
|
||||
printk(KERN_INFO "Boot Mode: %i\n", mmr & 0xF);
|
||||
|
||||
|
|
@ -980,7 +1032,7 @@ void __init setup_arch(char **cmdline_p)
|
|||
printk(KERN_INFO "Recovering from Watchdog event\n");
|
||||
else if (_bfin_swrst & RESET_SOFTWARE)
|
||||
printk(KERN_NOTICE "Reset caused by Software reset\n");
|
||||
|
||||
#endif
|
||||
printk(KERN_INFO "Blackfin support (C) 2004-2010 Analog Devices, Inc.\n");
|
||||
if (bfin_compiled_revid() == 0xffff)
|
||||
printk(KERN_INFO "Compiled for ADSP-%s Rev any, running on 0.%d\n", CPU, bfin_revid());
|
||||
|
|
@ -1060,10 +1112,12 @@ subsys_initcall(topology_init);
|
|||
|
||||
/* Get the input clock frequency */
|
||||
static u_long cached_clkin_hz = CONFIG_CLKIN_HZ;
|
||||
#ifndef CONFIG_BF60x
|
||||
static u_long get_clkin_hz(void)
|
||||
{
|
||||
return cached_clkin_hz;
|
||||
}
|
||||
#endif
|
||||
static int __init early_init_clkin_hz(char *buf)
|
||||
{
|
||||
cached_clkin_hz = simple_strtoul(buf, NULL, 0);
|
||||
|
|
@ -1075,6 +1129,7 @@ static int __init early_init_clkin_hz(char *buf)
|
|||
}
|
||||
early_param("clkin_hz=", early_init_clkin_hz);
|
||||
|
||||
#ifndef CONFIG_BF60x
|
||||
/* Get the voltage input multiplier */
|
||||
static u_long get_vco(void)
|
||||
{
|
||||
|
|
@ -1097,10 +1152,23 @@ static u_long get_vco(void)
|
|||
cached_vco *= msel;
|
||||
return cached_vco;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Get the Core clock */
|
||||
u_long get_cclk(void)
|
||||
{
|
||||
#ifdef CONFIG_BF60x
|
||||
struct clk *cclk;
|
||||
u_long cclk_rate;
|
||||
|
||||
cclk = clk_get(NULL, "CCLK");
|
||||
if (IS_ERR(cclk))
|
||||
return 0;
|
||||
|
||||
cclk_rate = clk_get_rate(cclk);
|
||||
clk_put(cclk);
|
||||
return cclk_rate;
|
||||
#else
|
||||
static u_long cached_cclk_pll_div, cached_cclk;
|
||||
u_long csel, ssel;
|
||||
|
||||
|
|
@ -1120,12 +1188,66 @@ u_long get_cclk(void)
|
|||
else
|
||||
cached_cclk = get_vco() >> csel;
|
||||
return cached_cclk;
|
||||
#endif
|
||||
}
|
||||
EXPORT_SYMBOL(get_cclk);
|
||||
|
||||
#ifdef CONFIG_BF60x
|
||||
/* Get the bf60x clock of SCLK0 domain */
|
||||
u_long get_sclk0(void)
|
||||
{
|
||||
struct clk *sclk0;
|
||||
u_long sclk0_rate;
|
||||
|
||||
sclk0 = clk_get(NULL, "SCLK0");
|
||||
if (IS_ERR(sclk0))
|
||||
return 0;
|
||||
|
||||
sclk0_rate = clk_get_rate(sclk0);
|
||||
clk_put(sclk0);
|
||||
return sclk0_rate;
|
||||
}
|
||||
EXPORT_SYMBOL(get_sclk0);
|
||||
|
||||
/* Get the bf60x clock of SCLK1 domain */
|
||||
u_long get_sclk1(void)
|
||||
{
|
||||
struct clk *sclk1;
|
||||
u_long sclk1_rate;
|
||||
|
||||
sclk1 = clk_get(NULL, "SCLK1");
|
||||
if (IS_ERR(sclk1))
|
||||
return 0;
|
||||
|
||||
sclk1_rate = clk_get_rate(sclk1);
|
||||
clk_put(sclk1);
|
||||
return sclk1_rate;
|
||||
}
|
||||
EXPORT_SYMBOL(get_sclk1);
|
||||
|
||||
/* Get the bf60x DRAM clock */
|
||||
u_long get_dclk(void)
|
||||
{
|
||||
struct clk *dclk;
|
||||
u_long dclk_rate;
|
||||
|
||||
dclk = clk_get(NULL, "DCLK");
|
||||
if (IS_ERR(dclk))
|
||||
return 0;
|
||||
|
||||
dclk_rate = clk_get_rate(dclk);
|
||||
clk_put(dclk);
|
||||
return dclk_rate;
|
||||
}
|
||||
EXPORT_SYMBOL(get_dclk);
|
||||
#endif
|
||||
|
||||
/* Get the System clock */
|
||||
u_long get_sclk(void)
|
||||
{
|
||||
#ifdef CONFIG_BF60x
|
||||
return get_sclk0();
|
||||
#else
|
||||
static u_long cached_sclk;
|
||||
u_long ssel;
|
||||
|
||||
|
|
@ -1146,6 +1268,7 @@ u_long get_sclk(void)
|
|||
|
||||
cached_sclk = get_vco() / ssel;
|
||||
return cached_sclk;
|
||||
#endif
|
||||
}
|
||||
EXPORT_SYMBOL(get_sclk);
|
||||
|
||||
|
|
|
|||
|
|
@ -15,9 +15,9 @@
|
|||
#include <asm/irq_handler.h>
|
||||
#include <asm/early_printk.h>
|
||||
|
||||
#define SHADOW_CONSOLE_START (0x500)
|
||||
#define SHADOW_CONSOLE_END (0x1000)
|
||||
#define SHADOW_CONSOLE_MAGIC_LOC (0x4F0)
|
||||
#define SHADOW_CONSOLE_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x500)
|
||||
#define SHADOW_CONSOLE_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x1000)
|
||||
#define SHADOW_CONSOLE_MAGIC_LOC (CONFIG_PHY_RAM_BASE_ADDRESS + 0x4F0)
|
||||
#define SHADOW_CONSOLE_MAGIC (0xDEADBEEF)
|
||||
|
||||
static __initdata char *shadow_console_buffer = (char *)SHADOW_CONSOLE_START;
|
||||
|
|
|
|||
|
|
@ -1141,7 +1141,8 @@ ENTRY(_schedule_and_signal_from_int)
|
|||
sti r0;
|
||||
|
||||
/* finish the userspace "atomic" functions for it */
|
||||
r1 = FIXED_CODE_END;
|
||||
r1.l = lo(FIXED_CODE_END);
|
||||
r1.h = hi(FIXED_CODE_END);
|
||||
r2 = [sp + PT_PC];
|
||||
cc = r1 <= r2;
|
||||
if cc jump .Lresume_userspace (bp);
|
||||
|
|
|
|||
|
|
@ -210,14 +210,12 @@ ENDPROC(__start)
|
|||
ENTRY(_real_start)
|
||||
/* Enable nested interrupts */
|
||||
[--sp] = reti;
|
||||
|
||||
/* watchdog off for now */
|
||||
p0.l = lo(WDOG_CTL);
|
||||
p0.h = hi(WDOG_CTL);
|
||||
r0 = 0xAD6(z);
|
||||
w[p0] = r0;
|
||||
ssync;
|
||||
|
||||
/* Pass the u-boot arguments to the global value command line */
|
||||
R0 = R7;
|
||||
call _cmdline_init;
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ void __init paging_init(void)
|
|||
|
||||
unsigned long zones_size[MAX_NR_ZONES] = {
|
||||
[0] = 0,
|
||||
[ZONE_DMA] = (end_mem - PAGE_OFFSET) >> PAGE_SHIFT,
|
||||
[ZONE_DMA] = (end_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> PAGE_SHIFT,
|
||||
[ZONE_NORMAL] = 0,
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
[ZONE_HIGHMEM] = 0,
|
||||
|
|
@ -60,7 +60,8 @@ void __init paging_init(void)
|
|||
|
||||
pr_debug("free_area_init -> start_mem is %#lx virtual_end is %#lx\n",
|
||||
PAGE_ALIGN(memory_start), end_mem);
|
||||
free_area_init(zones_size);
|
||||
free_area_init_node(0, zones_size,
|
||||
CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT, NULL);
|
||||
}
|
||||
|
||||
asmlinkage void __init init_pda(void)
|
||||
|
|
@ -75,9 +76,6 @@ asmlinkage void __init init_pda(void)
|
|||
valid pointers to it. */
|
||||
memset(&cpu_pda[cpu], 0, sizeof(cpu_pda[cpu]));
|
||||
|
||||
cpu_pda[0].next = &cpu_pda[1];
|
||||
cpu_pda[1].next = &cpu_pda[0];
|
||||
|
||||
#ifdef CONFIG_EXCEPTION_L1_SCRATCH
|
||||
cpu_pda[cpu].ex_stack = (unsigned long *)(L1_SCRATCH_START + \
|
||||
L1_SCRATCH_LENGTH);
|
||||
|
|
@ -109,10 +107,10 @@ void __init mem_init(void)
|
|||
totalram_pages = free_all_bootmem();
|
||||
|
||||
reservedpages = 0;
|
||||
for (tmp = 0; tmp < max_mapnr; tmp++)
|
||||
for (tmp = ARCH_PFN_OFFSET; tmp < max_mapnr; tmp++)
|
||||
if (PageReserved(pfn_to_page(tmp)))
|
||||
reservedpages++;
|
||||
freepages = max_mapnr - reservedpages;
|
||||
freepages = max_mapnr - ARCH_PFN_OFFSET - reservedpages;
|
||||
|
||||
/* do not count in kernel image between _rambase and _ramstart */
|
||||
reservedpages -= (_ramstart - _rambase) >> PAGE_SHIFT;
|
||||
|
|
@ -127,7 +125,7 @@ void __init mem_init(void)
|
|||
printk(KERN_INFO
|
||||
"Memory available: %luk/%luk RAM, "
|
||||
"(%uk init code, %uk kernel code, %uk data, %uk dma, %uk reserved)\n",
|
||||
(unsigned long) freepages << (PAGE_SHIFT-10), _ramend >> 10,
|
||||
(unsigned long) freepages << (PAGE_SHIFT-10), (_ramend - CONFIG_PHY_RAM_BASE_ADDRESS) >> 10,
|
||||
initk, codek, datak, DMA_UNCACHED_REGION >> 10, (reservedpages << (PAGE_SHIFT-10)));
|
||||
}
|
||||
|
||||
|
|
|
|||
Reference in New Issue