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authorTero Kristo <tero.kristo@nokia.com>2009-11-16 13:36:54 +0000
committerTony Lindgren <tony@atomide.com>2009-11-17 14:14:49 -0800
commit72f962fc7bc00f5ff4991912b889f87b464f7f1a (patch)
tree1ceaa76443aec354f5063f04d28b9acefbf6e4dd /arch
parent9346f48b26a4b48a7d56314bbb94e6b801e28316 (diff)
omap3: clock: Fixed dpll3_m2x2 rate calculation
Current calculation does not take into account any changes to M2 divisor, and thus when we change VDD2 OPP, dpll3_m2x2 rate does not change. Fixed by re-routing dpll3_m2x2 parent to dpll3_m2. Signed-off-by: Tero Kristo <tero.kristo@nokia.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap2/clock34xx.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index c8119781e00..9565c05bebd 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -489,9 +489,9 @@ static struct clk core_ck = {
static struct clk dpll3_m2x2_ck = {
.name = "dpll3_m2x2_ck",
.ops = &clkops_null,
- .parent = &dpll3_x2_ck,
+ .parent = &dpll3_m2_ck,
.clkdm_name = "dpll3_clkdm",
- .recalc = &followparent_recalc,
+ .recalc = &omap3_clkoutx2_recalc,
};
/* The PWRDN bit is apparently only available on 3430ES2 and above */