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authorPeter Zijlstra <peterz@infradead.org>2010-03-26 14:08:44 +0100
committerIngo Molnar <mingo@elte.hu>2010-03-26 15:47:24 +0100
commit11164cd4f6dab326a88bdf27f2f8f7c11977e91a (patch)
tree260a9f48f66cce8c5f4e23111ba6be8af6cfa578 /arch/x86/kernel/cpu/perf_event_p6.c
parentea8e61b7bbc4a2faef77db34eb2db2a2c2372ff6 (diff)
perf, x86: Add Nehelem PMU programming errata workaround
Implement the workaround for Intel Errata AAK100 and AAP53. Also, remove the Core-i7 name for Nehalem events since there are also Westmere based i7 chips. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Stephane Eranian <eranian@google.com> LKML-Reference: <1269608924.12097.147.camel@laptop> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel/cpu/perf_event_p6.c')
-rw-r--r--arch/x86/kernel/cpu/perf_event_p6.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_p6.c b/arch/x86/kernel/cpu/perf_event_p6.c
index 6ff4d01d880..877182c850d 100644
--- a/arch/x86/kernel/cpu/perf_event_p6.c
+++ b/arch/x86/kernel/cpu/perf_event_p6.c
@@ -66,7 +66,7 @@ static void p6_pmu_disable_all(void)
wrmsrl(MSR_P6_EVNTSEL0, val);
}
-static void p6_pmu_enable_all(void)
+static void p6_pmu_enable_all(int added)
{
unsigned long val;