|author||Chris Metcalf <email@example.com>||2011-02-28 16:37:34 -0500|
|committer||Chris Metcalf <firstname.lastname@example.org>||2011-03-10 13:17:53 -0500|
arch/tile: support 4KB page size as well as 64KB
The Tilera architecture traditionally supports 64KB page sizes to improve TLB utilization and improve performance when the hardware is being used primarily to run a single application. For more generic server scenarios, it can be beneficial to run with 4KB page sizes, so this commit allows that to be specified (by modifying the arch/tile/include/hv/pagesize.h header). As part of this change, we also re-worked the PTE management slightly so that PTE writes all go through a __set_pte() function where we can do some additional validation. The set_pte_order() function was eliminated since the "order" argument wasn't being used. One bug uncovered was in the PCI DMA code, which wasn't properly flushing the specified range. This was benign with 64KB pages, but with 4KB pages we were getting some larger flushes wrong. The per-cpu memory reservation code also needed updating to conform with the newer percpu stuff; before it always chose 64KB, and that was always correct, but with 4KB granularity we now have to pay closer attention and reserve the amount of memory that will be requested when the percpu code starts allocating. Signed-off-by: Chris Metcalf <email@example.com>
Diffstat (limited to 'arch/tile/Kconfig')
1 files changed, 0 insertions, 6 deletions
diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig
index eed0fc5dfe6..f3b78701c21 100644
@@ -202,12 +202,6 @@ config NODES_SHIFT
By default, 2, i.e. 2^2 == 4 DDR2 controllers.
In a system with more controllers, this value should be raised.
-# Need 16MB areas to enable hugetlb
-# See build-time check in arch/tile/mm/init.c.
- default 9
depends on !TILEGX
prompt "Memory split" if EXPERT