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authorDavid Daney <ddaney@caviumnetworks.com>2009-05-12 12:41:53 -0700
committerRalf Baechle <ralf@linux-mips.org>2009-06-17 11:06:26 +0100
commit41f0e4d041aa30507a34998c29d0b7ac0bede277 (patch)
tree7e84895b367ff6cfad682c6177c5ff706bb177c8 /arch/mips/mm/tlbex.c
parent95affdda9bfba0ac17025d48c622e1f30964e316 (diff)
MIPS: Allow R2 CPUs to turn off generation of 'ehb' instructions.
Some CPUs do not need ehb instructions after writing CP0 registers. By allowing ehb generation to be overridden in cpu-feature-overrides.h, we can save a few instructions in the TLB handler hot paths. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/tlbex.c')
-rw-r--r--arch/mips/mm/tlbex.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index d9a18b2b7f8..0e34faaadb5 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -259,7 +259,8 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
}
if (cpu_has_mips_r2) {
- uasm_i_ehb(p);
+ if (cpu_has_mips_r2_exec_hazard)
+ uasm_i_ehb(p);
tlbw(p);
return;
}