path: root/arch/mips/alchemy/Kconfig
diff options
authorManuel Lauss <manuel.lauss@googlemail.com>2009-06-06 14:09:55 +0200
committerRalf Baechle <ralf@linux-mips.org>2009-06-17 11:06:28 +0100
commit51e02b02e650183ff1277bcbad6a01d6ea0e9edb (patch)
tree413dfa5c93e2d01a42309f1cee6d6bf26d871962 /arch/mips/alchemy/Kconfig
parenteeb09e6545bf68222798ccf3f355560a9e406435 (diff)
MIPS: Alchemy: Rewrite GPIO support.
The current in-kernel Alchemy GPIO support is far too inflexible for all my use cases. To address this, the following changes are made: * create generic functions which deal with manipulating the on-chip GPIO1/2 blocks. Such functions are universally useful. * Macros for GPIO2 shared interrupt management and block control. * support for both built-in CONFIG_GPIOLIB and fast, inlined GPIO macros. If CONFIG_GPIOLIB is not enabled, provide linux gpio framework compatibility by directly inlining the GPIO1/2 functions. GPIO access is limited to on-chip ones and they can be accessed as documented in the datasheets (GPIO0-31 and 200-215). If CONFIG_GPIOLIB is selected, two (2) gpio_chip-s, one for GPIO1 and one for GPIO2, are registered. GPIOs can still be accessed by using the numberspace established in the databooks. However this is not yet flexible enough for my uses: My Alchemy systems have a documented "external" gpio interface (fixed, different numberspace) and can support a variety of baseboards, some of which are equipped with I2C gpio expanders. I want to be able to provide the default 16 GPIOs of the CPU board numbered as 0..15 and also support gpio expanders, if present, starting as gpio16. To achieve this, a new Kconfig symbol for Alchemy is introduced, CONFIG_ALCHEMY_GPIO_INDIRECT, which boards can enable to signal that they don't want the Alchemy numberspace exposed to the outside world, but instead want to provide their own. Boards are now respon- sible for providing the linux gpio interface glue code (either in a custom gpio.h header (in board include directory) or with gpio_chips). To make the board-specific inlined gpio functions work, the MIPS Makefile must be changed so that the mach-au1x00/gpio.h header is included _after_ the board headers, by moving the inclusion of the mach-au1x00/ to the end of the header list. See arch/mips/include/asm/mach-au1x00/gpio.h for more info. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Acked-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/alchemy/Kconfig')
1 files changed, 18 insertions, 1 deletions
diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig
index 8128aebfb15..00b498e97c8 100644
--- a/arch/mips/alchemy/Kconfig
+++ b/arch/mips/alchemy/Kconfig
@@ -1,3 +1,14 @@
+# au1000-style gpio
+config ALCHEMY_GPIO_AU1000
+ bool
+# select this in your board config if you don't want to use the gpio
+# namespace as documented in the manuals. In this case however you need
+# to create the necessary gpio_* functions in your board code/headers!
+# see arch/mips/include/asm/mach-au1x00/gpio.h for more information.
+ def_bool n
prompt "Machine type"
depends on MACH_ALCHEMY
@@ -108,22 +119,27 @@ endchoice
config SOC_AU1000
select SOC_AU1X00
+ select ALCHEMY_GPIO_AU1000
config SOC_AU1100
select SOC_AU1X00
+ select ALCHEMY_GPIO_AU1000
config SOC_AU1500
select SOC_AU1X00
+ select ALCHEMY_GPIO_AU1000
config SOC_AU1550
select SOC_AU1X00
+ select ALCHEMY_GPIO_AU1000
config SOC_AU1200
select SOC_AU1X00
+ select ALCHEMY_GPIO_AU1000
config SOC_AU1X00
@@ -134,4 +150,5 @@ config SOC_AU1X00
select SYS_HAS_CPU_MIPS32_R1