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authorLucas De Marchi <lucas.demarchi@profusion.mobi>2011-03-30 22:57:33 -0300
committerLucas De Marchi <lucas.demarchi@profusion.mobi>2011-03-31 11:26:23 -0300
commit25985edcedea6396277003854657b5f3cb31a628 (patch)
treef026e810210a2ee7290caeb737c23cb6472b7c38 /arch/m68k
parent6aba74f2791287ec407e0f92487a725a25908067 (diff)
Fix common misspellings
Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
Diffstat (limited to 'arch/m68k')
-rw-r--r--arch/m68k/atari/atakeyb.c2
-rw-r--r--arch/m68k/fpsp040/bindec.S2
-rw-r--r--arch/m68k/ifpsp060/src/fpsp.S10
-rw-r--r--arch/m68k/ifpsp060/src/pfpsp.S8
-rw-r--r--arch/m68k/include/asm/atariints.h2
-rw-r--r--arch/m68k/include/asm/bootstd.h2
-rw-r--r--arch/m68k/include/asm/commproc.h4
-rw-r--r--arch/m68k/include/asm/delay_no.h2
-rw-r--r--arch/m68k/include/asm/gpio.h2
-rw-r--r--arch/m68k/include/asm/m520xsim.h2
-rw-r--r--arch/m68k/include/asm/m523xsim.h2
-rw-r--r--arch/m68k/include/asm/m527xsim.h2
-rw-r--r--arch/m68k/include/asm/m5307sim.h2
-rw-r--r--arch/m68k/include/asm/m5407sim.h2
-rw-r--r--arch/m68k/include/asm/m68360_quicc.h2
-rw-r--r--arch/m68k/include/asm/mac_oss.h2
-rw-r--r--arch/m68k/include/asm/mac_via.h2
-rw-r--r--arch/m68k/include/asm/macintosh.h2
-rw-r--r--arch/m68k/include/asm/mcftimer.h2
-rw-r--r--arch/m68k/kernel/head.S12
-rw-r--r--arch/m68k/kernel/vmlinux.lds_no.S2
-rw-r--r--arch/m68k/platform/523x/config.c2
-rw-r--r--arch/m68k/platform/5272/intc.c2
-rw-r--r--arch/m68k/platform/527x/config.c2
-rw-r--r--arch/m68k/platform/528x/config.c2
-rw-r--r--arch/m68k/platform/coldfire/cache.c2
-rw-r--r--arch/m68k/platform/coldfire/entry.S2
-rw-r--r--arch/m68k/platform/coldfire/head.S2
-rw-r--r--arch/m68k/platform/coldfire/intc.c2
-rw-r--r--arch/m68k/platform/coldfire/sltimers.c2
-rw-r--r--arch/m68k/q40/README2
31 files changed, 44 insertions, 44 deletions
diff --git a/arch/m68k/atari/atakeyb.c b/arch/m68k/atari/atakeyb.c
index 5890897d28b..b995513d527 100644
--- a/arch/m68k/atari/atakeyb.c
+++ b/arch/m68k/atari/atakeyb.c
@@ -130,7 +130,7 @@ KEYBOARD_STATE kb_state;
* it's really hard to decide whether they're mouse or keyboard bytes. Since
* overruns usually occur when moving the Atari mouse rapidly, they're seen as
* mouse bytes here. If this is wrong, only a make code of the keyboard gets
- * lost, which isn't too bad. Loosing a break code would be disastrous,
+ * lost, which isn't too bad. Losing a break code would be disastrous,
* because then the keyboard repeat strikes...
*/
diff --git a/arch/m68k/fpsp040/bindec.S b/arch/m68k/fpsp040/bindec.S
index 72f1159cb80..f2e79523104 100644
--- a/arch/m68k/fpsp040/bindec.S
+++ b/arch/m68k/fpsp040/bindec.S
@@ -609,7 +609,7 @@ do_fint:
| A6. This test occurs only on the first pass. If the
| result is exactly 10^LEN, decrement ILOG and divide
| the mantissa by 10. The calculation of 10^LEN cannot
-| be inexact, since all powers of ten upto 10^27 are exact
+| be inexact, since all powers of ten up to 10^27 are exact
| in extended precision, so the use of a previous power-of-ten
| table will introduce no error.
|
diff --git a/arch/m68k/ifpsp060/src/fpsp.S b/arch/m68k/ifpsp060/src/fpsp.S
index 26e85e2b7a5..78cb60f5bb4 100644
--- a/arch/m68k/ifpsp060/src/fpsp.S
+++ b/arch/m68k/ifpsp060/src/fpsp.S
@@ -11813,7 +11813,7 @@ fmul_unfl_ena:
bne.b fmul_unfl_ena_sd # no, sgl or dbl
# if the rnd mode is anything but RZ, then we have to re-do the above
-# multiplication becuase we used RZ for all.
+# multiplication because we used RZ for all.
fmov.l L_SCR3(%a6),%fpcr # set FPCR
fmul_unfl_ena_cont:
@@ -18095,7 +18095,7 @@ fscc_mem_op:
rts
-# addresing mode is post-increment. write the result byte. if the write
+# addressing mode is post-increment. write the result byte. if the write
# fails then don't update the address register. if write passes then
# call inc_areg() to update the address register.
fscc_mem_inc:
@@ -20876,7 +20876,7 @@ dst_get_dupper:
swap %d0 # d0 now in upper word
lsl.l &0x4,%d0 # d0 in proper place for dbl prec exp
tst.b FTEMP_EX(%a0) # test sign
- bpl.b dst_get_dman # if postive, go process mantissa
+ bpl.b dst_get_dman # if positive, go process mantissa
bset &0x1f,%d0 # if negative, set sign
dst_get_dman:
mov.l FTEMP_HI(%a0),%d1 # get ms mantissa
@@ -22943,7 +22943,7 @@ tbl_ovfl_result:
# FP_SRC(a6) = packed operand now as a binary FP number #
# #
# ALGORITHM *********************************************************** #
-# Get the correct <ea> whihc is the value on the exception stack #
+# Get the correct <ea> which is the value on the exception stack #
# frame w/ maybe a correction factor if the <ea> is -(an) or (an)+. #
# Then, fetch the operand from memory. If the fetch fails, exit #
# through facc_in_x(). #
@@ -24096,7 +24096,7 @@ do_fint12:
# A6. This test occurs only on the first pass. If the
# result is exactly 10^LEN, decrement ILOG and divide
# the mantissa by 10. The calculation of 10^LEN cannot
-# be inexact, since all powers of ten upto 10^27 are exact
+# be inexact, since all powers of ten up to 10^27 are exact
# in extended precision, so the use of a previous power-of-ten
# table will introduce no error.
#
diff --git a/arch/m68k/ifpsp060/src/pfpsp.S b/arch/m68k/ifpsp060/src/pfpsp.S
index e71ba0ab013..4aedef973cf 100644
--- a/arch/m68k/ifpsp060/src/pfpsp.S
+++ b/arch/m68k/ifpsp060/src/pfpsp.S
@@ -7777,7 +7777,7 @@ dst_get_dupper:
swap %d0 # d0 now in upper word
lsl.l &0x4,%d0 # d0 in proper place for dbl prec exp
tst.b FTEMP_EX(%a0) # test sign
- bpl.b dst_get_dman # if postive, go process mantissa
+ bpl.b dst_get_dman # if positive, go process mantissa
bset &0x1f,%d0 # if negative, set sign
dst_get_dman:
mov.l FTEMP_HI(%a0),%d1 # get ms mantissa
@@ -8244,7 +8244,7 @@ fmul_unfl_ena:
bne.b fmul_unfl_ena_sd # no, sgl or dbl
# if the rnd mode is anything but RZ, then we have to re-do the above
-# multiplication becuase we used RZ for all.
+# multiplication because we used RZ for all.
fmov.l L_SCR3(%a6),%fpcr # set FPCR
fmul_unfl_ena_cont:
@@ -12903,7 +12903,7 @@ store_fpreg_7:
# FP_SRC(a6) = packed operand now as a binary FP number #
# #
# ALGORITHM *********************************************************** #
-# Get the correct <ea> whihc is the value on the exception stack #
+# Get the correct <ea> which is the value on the exception stack #
# frame w/ maybe a correction factor if the <ea> is -(an) or (an)+. #
# Then, fetch the operand from memory. If the fetch fails, exit #
# through facc_in_x(). #
@@ -14056,7 +14056,7 @@ do_fint12:
# A6. This test occurs only on the first pass. If the
# result is exactly 10^LEN, decrement ILOG and divide
# the mantissa by 10. The calculation of 10^LEN cannot
-# be inexact, since all powers of ten upto 10^27 are exact
+# be inexact, since all powers of ten up to 10^27 are exact
# in extended precision, so the use of a previous power-of-ten
# table will introduce no error.
#
diff --git a/arch/m68k/include/asm/atariints.h b/arch/m68k/include/asm/atariints.h
index f597892e43a..656bbbf5a6f 100644
--- a/arch/m68k/include/asm/atariints.h
+++ b/arch/m68k/include/asm/atariints.h
@@ -146,7 +146,7 @@ static inline void clear_mfp_bit( unsigned irq, int type )
/*
* {en,dis}able_irq have the usual semantics of temporary blocking the
- * interrupt, but not loosing requests that happen between disabling and
+ * interrupt, but not losing requests that happen between disabling and
* enabling. This is done with the MFP mask registers.
*/
diff --git a/arch/m68k/include/asm/bootstd.h b/arch/m68k/include/asm/bootstd.h
index bdc1a4ac4fe..e518f5a575b 100644
--- a/arch/m68k/include/asm/bootstd.h
+++ b/arch/m68k/include/asm/bootstd.h
@@ -31,7 +31,7 @@
#define __BN_flash_write_range 20
/* Calling conventions compatible to (uC)linux/68k
- * We use simmilar macros to call into the bootloader as for uClinux
+ * We use similar macros to call into the bootloader as for uClinux
*/
#define __bsc_return(type, res) \
diff --git a/arch/m68k/include/asm/commproc.h b/arch/m68k/include/asm/commproc.h
index edf5eb6c08d..a73998528d2 100644
--- a/arch/m68k/include/asm/commproc.h
+++ b/arch/m68k/include/asm/commproc.h
@@ -88,7 +88,7 @@ typedef struct cpm_buf_desc {
/* rx bd status/control bits */
-#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
+#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor in table */
#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame OR control char */
@@ -96,7 +96,7 @@ typedef struct cpm_buf_desc {
#define BD_SC_FIRST ((ushort)0x0400) /* 1st buffer in an HDLC frame */
#define BD_SC_ADDR ((ushort)0x0400) /* 1st byte is a multidrop address */
-#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
+#define BD_SC_CM ((ushort)0x0200) /* Continuous mode */
#define BD_SC_ID ((ushort)0x0100) /* Received too many idles */
#define BD_SC_AM ((ushort)0x0080) /* Multidrop address match */
diff --git a/arch/m68k/include/asm/delay_no.h b/arch/m68k/include/asm/delay_no.h
index 55cbd6294ab..c3a0edc90f2 100644
--- a/arch/m68k/include/asm/delay_no.h
+++ b/arch/m68k/include/asm/delay_no.h
@@ -16,7 +16,7 @@ static inline void __delay(unsigned long loops)
* long word alignment which is the faster version.
* The 0x4a8e is of course a 'tstl %fp' instruction. This is better
* than using a NOP (0x4e71) instruction because it executes in one
- * cycle not three and doesn't allow for an arbitary delay waiting
+ * cycle not three and doesn't allow for an arbitrary delay waiting
* for bus cycles to finish. Also fp/a6 isn't likely to cause a
* stall waiting for the register to become valid if such is added
* to the coldfire at some stage.
diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h
index c64c7b74cf8..b2046839f4b 100644
--- a/arch/m68k/include/asm/gpio.h
+++ b/arch/m68k/include/asm/gpio.h
@@ -31,7 +31,7 @@
* GPIOs in a single control area, others have some GPIOs implemented in
* different modules.
*
- * This implementation attempts accomodate the differences while presenting
+ * This implementation attempts accommodate the differences while presenting
* a generic interface that will optimize to as few instructions as possible.
*/
#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index 55d5a4c5fe0..b6bf2c518ba 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -157,7 +157,7 @@
#define MCFFEC_SIZE 0x800 /* Register set size */
/*
- * Reset Controll Unit.
+ * Reset Control Unit.
*/
#define MCF_RCR 0xFC0A0000
#define MCF_RSR 0xFC0A0001
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 8996df62ede..6235921eca4 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -48,7 +48,7 @@
#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */
/*
- * Reset Controll Unit (relative to IPSBAR).
+ * Reset Control Unit (relative to IPSBAR).
*/
#define MCF_RCR 0x110000
#define MCF_RSR 0x110001
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 74855a66c05..758810ef91e 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -283,7 +283,7 @@
#endif
/*
- * Reset Controll Unit (relative to IPSBAR).
+ * Reset Control Unit (relative to IPSBAR).
*/
#define MCF_RCR 0x110000
#define MCF_RSR 0x110001
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index 4c94c01f36c..8f8609fcc9b 100644
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -29,7 +29,7 @@
#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */
#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */
-#define MCFSIM_PLLCR 0x08 /* PLL Controll Reg*/
+#define MCFSIM_PLLCR 0x08 /* PLL Control Reg*/
#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index 762c58c8905..51e00b00b8a 100644
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -29,7 +29,7 @@
#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */
#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */
-#define MCFSIM_PLLCR 0x08 /* PLL Controll Reg*/
+#define MCFSIM_PLLCR 0x08 /* PLL Control Reg*/
#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
diff --git a/arch/m68k/include/asm/m68360_quicc.h b/arch/m68k/include/asm/m68360_quicc.h
index 6d40f4d18e1..59414cc108d 100644
--- a/arch/m68k/include/asm/m68360_quicc.h
+++ b/arch/m68k/include/asm/m68360_quicc.h
@@ -32,7 +32,7 @@ struct user_data {
/* BASE + 0x000: user data memory */
volatile unsigned char udata_bd_ucode[0x400]; /*user data bd's Ucode*/
volatile unsigned char udata_bd[0x200]; /*user data Ucode */
- volatile unsigned char ucode_ext[0x100]; /*Ucode Extention ram */
+ volatile unsigned char ucode_ext[0x100]; /*Ucode Extension ram */
volatile unsigned char RESERVED1[0x500]; /* Reserved area */
};
#else
diff --git a/arch/m68k/include/asm/mac_oss.h b/arch/m68k/include/asm/mac_oss.h
index 7221f725193..3cf2b6ed685 100644
--- a/arch/m68k/include/asm/mac_oss.h
+++ b/arch/m68k/include/asm/mac_oss.h
@@ -61,7 +61,7 @@
/*
* OSS Interrupt levels for various sub-systems
*
- * This mapping is layed out with two things in mind: first, we try to keep
+ * This mapping is laid out with two things in mind: first, we try to keep
* things on their own levels to avoid having to do double-dispatches. Second,
* the levels match as closely as possible the alternate IRQ mapping mode (aka
* "A/UX mode") available on some VIA machines.
diff --git a/arch/m68k/include/asm/mac_via.h b/arch/m68k/include/asm/mac_via.h
index 39afb438b65..a59665e1d41 100644
--- a/arch/m68k/include/asm/mac_via.h
+++ b/arch/m68k/include/asm/mac_via.h
@@ -204,7 +204,7 @@
#define vT2CL 0x1000 /* [VIA only] Timer two counter low. */
#define vT2CH 0x1200 /* [VIA only] Timer two counter high. */
#define vSR 0x1400 /* [VIA only] Shift register. */
-#define vACR 0x1600 /* [VIA only] Auxilary control register. */
+#define vACR 0x1600 /* [VIA only] Auxiliary control register. */
#define vPCR 0x1800 /* [VIA only] Peripheral control register. */
/* CHRP sez never ever to *write* this.
* Mac family says never to *change* this.
diff --git a/arch/m68k/include/asm/macintosh.h b/arch/m68k/include/asm/macintosh.h
index 50db3591ca1..c2a1c5eac1a 100644
--- a/arch/m68k/include/asm/macintosh.h
+++ b/arch/m68k/include/asm/macintosh.h
@@ -14,7 +14,7 @@ extern void mac_init_IRQ(void);
extern int mac_irq_pending(unsigned int);
/*
- * Floppy driver magic hook - probably shouldnt be here
+ * Floppy driver magic hook - probably shouldn't be here
*/
extern void via1_set_head(int);
diff --git a/arch/m68k/include/asm/mcftimer.h b/arch/m68k/include/asm/mcftimer.h
index 92b276fe824..351c2723787 100644
--- a/arch/m68k/include/asm/mcftimer.h
+++ b/arch/m68k/include/asm/mcftimer.h
@@ -27,7 +27,7 @@
/*
* Bit definitions for the Timer Mode Register (TMR).
- * Register bit flags are common accross ColdFires.
+ * Register bit flags are common across ColdFires.
*/
#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */
#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */
diff --git a/arch/m68k/kernel/head.S b/arch/m68k/kernel/head.S
index ef54128baa0..27622b3273c 100644
--- a/arch/m68k/kernel/head.S
+++ b/arch/m68k/kernel/head.S
@@ -134,7 +134,7 @@
* Thanks to a small helping routine enabling the mmu got quite simple
* and there is only one way left. mmu_engage makes a complete a new mapping
* that only includes the absolute necessary to be able to jump to the final
- * postion and to restore the original mapping.
+ * position and to restore the original mapping.
* As this code doesn't need a transparent translation register anymore this
* means all registers are free to be used by machines that needs them for
* other purposes.
@@ -969,7 +969,7 @@ L(mmu_init_amiga):
is_not_040_or_060(1f)
/*
- * 040: Map the 16Meg range physical 0x0 upto logical 0x8000.0000
+ * 040: Map the 16Meg range physical 0x0 up to logical 0x8000.0000
*/
mmu_map #0x80000000,#0,#0x01000000,#_PAGE_NOCACHE_S
/*
@@ -982,7 +982,7 @@ L(mmu_init_amiga):
1:
/*
- * 030: Map the 32Meg range physical 0x0 upto logical 0x8000.0000
+ * 030: Map the 32Meg range physical 0x0 up to logical 0x8000.0000
*/
mmu_map #0x80000000,#0,#0x02000000,#_PAGE_NOCACHE030
mmu_map_tt #1,#0x40000000,#0x20000000,#_PAGE_NOCACHE030
@@ -1074,7 +1074,7 @@ L(notq40):
is_040(1f)
/*
- * 030: Map the 32Meg range physical 0x0 upto logical 0xf000.0000
+ * 030: Map the 32Meg range physical 0x0 up to logical 0xf000.0000
*/
mmu_map #0xf0000000,#0,#0x02000000,#_PAGE_NOCACHE030
@@ -1082,7 +1082,7 @@ L(notq40):
1:
/*
- * 040: Map the 16Meg range physical 0x0 upto logical 0xf000.0000
+ * 040: Map the 16Meg range physical 0x0 up to logical 0xf000.0000
*/
mmu_map #0xf0000000,#0,#0x01000000,#_PAGE_NOCACHE_S
@@ -3078,7 +3078,7 @@ func_start serial_putc,%d0/%d1/%a0/%a1
/*
* If the loader gave us a board type then we can use that to
* select an appropriate output routine; otherwise we just use
- * the Bug code. If we haev to use the Bug that means the Bug
+ * the Bug code. If we have to use the Bug that means the Bug
* workspace has to be valid, which means the Bug has to use
* the SRAM, which is non-standard.
*/
diff --git a/arch/m68k/kernel/vmlinux.lds_no.S b/arch/m68k/kernel/vmlinux.lds_no.S
index 47e15ebfd89..f4d715cdca0 100644
--- a/arch/m68k/kernel/vmlinux.lds_no.S
+++ b/arch/m68k/kernel/vmlinux.lds_no.S
@@ -3,7 +3,7 @@
*
* (C) Copyright 2002-2006, Greg Ungerer <gerg@snapgear.com>
*
- * This linker script is equiped to build either ROM loaded or RAM
+ * This linker script is equipped to build either ROM loaded or RAM
* run kernels.
*/
diff --git a/arch/m68k/platform/523x/config.c b/arch/m68k/platform/523x/config.c
index 418a76feb1e..71f4436ec80 100644
--- a/arch/m68k/platform/523x/config.c
+++ b/arch/m68k/platform/523x/config.c
@@ -3,7 +3,7 @@
/*
* linux/arch/m68knommu/platform/523x/config.c
*
- * Sub-architcture dependant initialization code for the Freescale
+ * Sub-architcture dependent initialization code for the Freescale
* 523x CPUs.
*
* Copyright (C) 1999-2005, Greg Ungerer (gerg@snapgear.com)
diff --git a/arch/m68k/platform/5272/intc.c b/arch/m68k/platform/5272/intc.c
index 43e6e96f087..7e715dfe281 100644
--- a/arch/m68k/platform/5272/intc.c
+++ b/arch/m68k/platform/5272/intc.c
@@ -33,7 +33,7 @@
*
* Note that the external interrupts are edge triggered (unlike the
* internal interrupt sources which are level triggered). Which means
- * they also need acknowledgeing via acknowledge bits.
+ * they also need acknowledging via acknowledge bits.
*/
struct irqmap {
unsigned char icr;
diff --git a/arch/m68k/platform/527x/config.c b/arch/m68k/platform/527x/config.c
index fa359593b61..3ebc769cefd 100644
--- a/arch/m68k/platform/527x/config.c
+++ b/arch/m68k/platform/527x/config.c
@@ -3,7 +3,7 @@
/*
* linux/arch/m68knommu/platform/527x/config.c
*
- * Sub-architcture dependant initialization code for the Freescale
+ * Sub-architcture dependent initialization code for the Freescale
* 5270/5271 CPUs.
*
* Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com)
diff --git a/arch/m68k/platform/528x/config.c b/arch/m68k/platform/528x/config.c
index ac39fc66121..7abe77a2f3e 100644
--- a/arch/m68k/platform/528x/config.c
+++ b/arch/m68k/platform/528x/config.c
@@ -3,7 +3,7 @@
/*
* linux/arch/m68knommu/platform/528x/config.c
*
- * Sub-architcture dependant initialization code for the Freescale
+ * Sub-architcture dependent initialization code for the Freescale
* 5280, 5281 and 5282 CPUs.
*
* Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com)
diff --git a/arch/m68k/platform/coldfire/cache.c b/arch/m68k/platform/coldfire/cache.c
index 235d3c4f4f0..71beeaf0c5c 100644
--- a/arch/m68k/platform/coldfire/cache.c
+++ b/arch/m68k/platform/coldfire/cache.c
@@ -1,7 +1,7 @@
/***************************************************************************/
/*
- * cache.c -- general ColdFire Cache maintainence code
+ * cache.c -- general ColdFire Cache maintenance code
*
* Copyright (C) 2010, Greg Ungerer (gerg@snapgear.com)
*/
diff --git a/arch/m68k/platform/coldfire/entry.S b/arch/m68k/platform/coldfire/entry.S
index 5837cf080b6..eab63f09965 100644
--- a/arch/m68k/platform/coldfire/entry.S
+++ b/arch/m68k/platform/coldfire/entry.S
@@ -163,7 +163,7 @@ Lsignal_return:
/*
* This is the generic interrupt handler (for all hardware interrupt
- * sources). Calls upto high level code to do all the work.
+ * sources). Calls up to high level code to do all the work.
*/
ENTRY(inthandler)
SAVE_ALL
diff --git a/arch/m68k/platform/coldfire/head.S b/arch/m68k/platform/coldfire/head.S
index 129bff4956b..6ae91a49918 100644
--- a/arch/m68k/platform/coldfire/head.S
+++ b/arch/m68k/platform/coldfire/head.S
@@ -20,7 +20,7 @@
/*
* If we don't have a fixed memory size, then lets build in code
- * to auto detect the DRAM size. Obviously this is the prefered
+ * to auto detect the DRAM size. Obviously this is the preferred
* method, and should work for most boards. It won't work for those
* that do not have their RAM starting at address 0, and it only
* works on SDRAM (not boards fitted with SRAM).
diff --git a/arch/m68k/platform/coldfire/intc.c b/arch/m68k/platform/coldfire/intc.c
index c28a6ed6cb2..0bbb414856e 100644
--- a/arch/m68k/platform/coldfire/intc.c
+++ b/arch/m68k/platform/coldfire/intc.c
@@ -37,7 +37,7 @@ unsigned char mcf_irq2imr[NR_IRQS];
/*
* In the early version 2 core ColdFire parts the IMR register was 16 bits
* in size. Version 3 (and later version 2) core parts have a 32 bit
- * sized IMR register. Provide some size independant methods to access the
+ * sized IMR register. Provide some size independent methods to access the
* IMR register.
*/
#ifdef MCFSIM_IMR_IS_16BITS
diff --git a/arch/m68k/platform/coldfire/sltimers.c b/arch/m68k/platform/coldfire/sltimers.c
index 0a1b937c3e1..6a85daf9a7f 100644
--- a/arch/m68k/platform/coldfire/sltimers.c
+++ b/arch/m68k/platform/coldfire/sltimers.c
@@ -106,7 +106,7 @@ static cycle_t mcfslt_read_clk(struct clocksource *cs)
cycles = mcfslt_cnt;
local_irq_restore(flags);
- /* substract because slice timers count down */
+ /* subtract because slice timers count down */
return cycles - scnt;
}
diff --git a/arch/m68k/q40/README b/arch/m68k/q40/README
index f877b724979..b26d5f55e91 100644
--- a/arch/m68k/q40/README
+++ b/arch/m68k/q40/README
@@ -89,7 +89,7 @@ The main interrupt register IIRQ_REG will indicate whether an IRQ was internal
or from some ISA devices, EIRQ_REG can distinguish up to 8 ISA IRQs.
The Q40 custom chip is programmable to provide 2 periodic timers:
- - 50 or 200 Hz - level 2, !!THIS CANT BE DISABLED!!
+ - 50 or 200 Hz - level 2, !!THIS CAN'T BE DISABLED!!
- 10 or 20 KHz - level 4, used for dma-sound
Linux uses the 200 Hz interrupt for timer and beep by default.