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authorLucas De Marchi <lucas.demarchi@profusion.mobi>2011-03-30 22:57:33 -0300
committerLucas De Marchi <lucas.demarchi@profusion.mobi>2011-03-31 11:26:23 -0300
commit25985edcedea6396277003854657b5f3cb31a628 (patch)
treef026e810210a2ee7290caeb737c23cb6472b7c38 /arch/arm
parent6aba74f2791287ec407e0f92487a725a25908067 (diff)
Fix common misspellings
Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/Kconfig-nommu2
-rw-r--r--arch/arm/common/pl330.c4
-rw-r--r--arch/arm/include/asm/fpstate.h2
-rw-r--r--arch/arm/include/asm/glue-cache.h2
-rw-r--r--arch/arm/include/asm/glue.h4
-rw-r--r--arch/arm/include/asm/hardware/pl080.h2
-rw-r--r--arch/arm/include/asm/system.h2
-rw-r--r--arch/arm/include/asm/ucontext.h2
-rw-r--r--arch/arm/kernel/swp_emulate.c2
-rw-r--r--arch/arm/mach-at91/board-carmeva.c2
-rw-r--r--arch/arm/mach-at91/include/mach/at91_mci.h2
-rw-r--r--arch/arm/mach-at91/include/mach/gpio.h2
-rw-r--r--arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c6
-rw-r--r--arch/arm/mach-bcmring/dma.c4
-rw-r--r--arch/arm/mach-bcmring/include/csp/dmacHw.h6
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h2
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h2
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h4
-rw-r--r--arch/arm/mach-bcmring/include/mach/reg_umi.h2
-rw-r--r--arch/arm/mach-davinci/board-neuros-osd2.c2
-rw-r--r--arch/arm/mach-davinci/cpufreq.c2
-rw-r--r--arch/arm/mach-davinci/da850.c2
-rw-r--r--arch/arm/mach-davinci/dm355.c2
-rw-r--r--arch/arm/mach-davinci/dm644x.c2
-rw-r--r--arch/arm/mach-davinci/include/mach/cputype.h2
-rw-r--r--arch/arm/mach-ep93xx/gpio.c2
-rw-r--r--arch/arm/mach-exynos4/include/mach/gpio.h2
-rw-r--r--arch/arm/mach-exynos4/mct.c2
-rw-r--r--arch/arm/mach-exynos4/setup-sdhci-gpio.c4
-rw-r--r--arch/arm/mach-exynos4/setup-sdhci.c2
-rw-r--r--arch/arm/mach-iop13xx/pci.c4
-rw-r--r--arch/arm/mach-kirkwood/tsx1x-common.c2
-rw-r--r--arch/arm/mach-lpc32xx/pm.c2
-rw-r--r--arch/arm/mach-mmp/time.c2
-rw-r--r--arch/arm/mach-msm/acpuclock-arm11.c2
-rw-r--r--arch/arm/mach-msm/scm.c2
-rw-r--r--arch/arm/mach-omap1/ams-delta-fiq-handler.S2
-rw-r--r--arch/arm/mach-omap1/board-sx1.c2
-rw-r--r--arch/arm/mach-omap1/devices.c2
-rw-r--r--arch/arm/mach-omap1/include/mach/ams-delta-fiq.h2
-rw-r--r--arch/arm/mach-omap2/board-igep0020.c2
-rw-r--r--arch/arm/mach-omap2/board-igep0030.c2
-rw-r--r--arch/arm/mach-omap2/clockdomain.c2
-rw-r--r--arch/arm/mach-omap2/clockdomain.h2
-rw-r--r--arch/arm/mach-omap2/cpuidle34xx.c4
-rw-r--r--arch/arm/mach-omap2/devices.c6
-rw-r--r--arch/arm/mach-omap2/dma.c2
-rw-r--r--arch/arm/mach-omap2/gpio.c2
-rw-r--r--arch/arm/mach-omap2/hsmmc.c2
-rw-r--r--arch/arm/mach-omap2/mcbsp.c2
-rw-r--r--arch/arm/mach-omap2/mux.c2
-rw-r--r--arch/arm/mach-omap2/mux2430.h2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c2
-rw-r--r--arch/arm/mach-omap2/omap_phy_internal.c4
-rw-r--r--arch/arm/mach-omap2/omap_twl.c2
-rw-r--r--arch/arm/mach-omap2/powerdomain.c2
-rw-r--r--arch/arm/mach-omap2/powerdomain.h2
-rw-r--r--arch/arm/mach-omap2/powerdomains3xxx_data.c2
-rw-r--r--arch/arm/mach-omap2/smartreflex.c2
-rw-r--r--arch/arm/mach-omap2/voltage.c4
-rw-r--r--arch/arm/mach-orion5x/addr-map.c2
-rw-r--r--arch/arm/mach-orion5x/net2big-setup.c2
-rw-r--r--arch/arm/mach-orion5x/ts209-setup.c2
-rw-r--r--arch/arm/mach-orion5x/ts409-setup.c2
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa3xx-regs.h2
-rw-r--r--arch/arm/mach-pxa/include/mach/zeus.h2
-rw-r--r--arch/arm/mach-pxa/mioa701.c2
-rw-r--r--arch/arm/mach-s3c2410/include/mach/dma.h2
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-mem.h2
-rw-r--r--arch/arm/mach-s3c2410/mach-n30.c2
-rw-r--r--arch/arm/mach-s3c2440/mach-mini2440.c2
-rw-r--r--arch/arm/mach-s3c64xx/dma.c2
-rw-r--r--arch/arm/mach-s5pc100/include/mach/regs-fb.h2
-rw-r--r--arch/arm/mach-s5pc100/setup-sdhci.c2
-rw-r--r--arch/arm/mach-s5pv210/include/mach/gpio.h2
-rw-r--r--arch/arm/mach-s5pv210/setup-sdhci-gpio.c4
-rw-r--r--arch/arm/mach-s5pv210/setup-sdhci.c2
-rw-r--r--arch/arm/mach-sa1100/Makefile2
-rw-r--r--arch/arm/mach-sa1100/cpu-sa1100.c2
-rw-r--r--arch/arm/mach-sa1100/include/mach/SA-1100.h2
-rw-r--r--arch/arm/mach-sa1100/jornada720_ssp.c4
-rw-r--r--arch/arm/mach-tegra/dma.c4
-rw-r--r--arch/arm/mach-tegra/include/mach/dma.h4
-rw-r--r--arch/arm/mach-u300/clock.c6
-rw-r--r--arch/arm/mach-ux500/board-mop500.c2
-rw-r--r--arch/arm/mach-ux500/include/mach/db8500-regs.h10
-rw-r--r--arch/arm/mm/cache-v4wb.S2
-rw-r--r--arch/arm/mm/cache-v4wt.S2
-rw-r--r--arch/arm/mm/cache-v7.S2
-rw-r--r--arch/arm/mm/proc-arm1020.S2
-rw-r--r--arch/arm/mm/proc-arm1020e.S2
-rw-r--r--arch/arm/mm/proc-arm1022.S2
-rw-r--r--arch/arm/mm/proc-arm1026.S2
-rw-r--r--arch/arm/mm/proc-arm720.S2
-rw-r--r--arch/arm/mm/proc-arm920.S2
-rw-r--r--arch/arm/mm/proc-arm922.S2
-rw-r--r--arch/arm/mm/proc-arm925.S2
-rw-r--r--arch/arm/mm/proc-macros.S2
-rw-r--r--arch/arm/mm/proc-v6.S4
-rw-r--r--arch/arm/mm/proc-v7.S2
-rw-r--r--arch/arm/plat-mxc/cpufreq.c2
-rw-r--r--arch/arm/plat-mxc/include/mach/entry-macro.S4
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc_nand.h2
-rw-r--r--arch/arm/plat-omap/devices.c2
-rw-r--r--arch/arm/plat-omap/dma.c4
-rw-r--r--arch/arm/plat-omap/include/plat/gpio.h2
-rw-r--r--arch/arm/plat-omap/include/plat/gpmc.h2
-rw-r--r--arch/arm/plat-omap/mcbsp.c2
-rw-r--r--arch/arm/plat-pxa/include/plat/mfp.h2
-rw-r--r--arch/arm/plat-s3c24xx/Makefile2
-rw-r--r--arch/arm/plat-s3c24xx/cpu-freq.c2
-rw-r--r--arch/arm/plat-s3c24xx/dma.c2
-rw-r--r--arch/arm/plat-s5p/irq-gpioint.c2
-rw-r--r--arch/arm/plat-samsung/include/plat/clock.h2
-rw-r--r--arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h2
-rw-r--r--arch/arm/plat-samsung/include/plat/gpio-cfg.h6
-rw-r--r--arch/arm/plat-samsung/include/plat/gpio-core.h2
-rw-r--r--arch/arm/plat-samsung/include/plat/sdhci.h4
-rw-r--r--arch/arm/plat-samsung/s3c-pl330.c2
-rw-r--r--arch/arm/plat-spear/include/plat/clock.h2
121 files changed, 152 insertions, 152 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5b9f78b570e..fdc9d4dbf85 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -694,7 +694,7 @@ config ARCH_S3C2410
the Samsung SMDK2410 development board (and derivatives).
Note, the S3C2416 and the S3C2450 are so close that they even share
- the same SoC ID code. This means that there is no seperate machine
+ the same SoC ID code. This means that there is no separate machine
directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
config ARCH_S3C64XX
diff --git a/arch/arm/Kconfig-nommu b/arch/arm/Kconfig-nommu
index 901e6dff843..2cef8e13f9f 100644
--- a/arch/arm/Kconfig-nommu
+++ b/arch/arm/Kconfig-nommu
@@ -34,7 +34,7 @@ config PROCESSOR_ID
used instead of the auto-probing which utilizes the register.
config REMAP_VECTORS_TO_RAM
- bool 'Install vectors to the begining of RAM' if DRAM_BASE
+ bool 'Install vectors to the beginning of RAM' if DRAM_BASE
depends on DRAM_BASE
help
The kernel needs to change the hardware exception vectors.
diff --git a/arch/arm/common/pl330.c b/arch/arm/common/pl330.c
index 8f0f86db360..97912fa4878 100644
--- a/arch/arm/common/pl330.c
+++ b/arch/arm/common/pl330.c
@@ -1045,7 +1045,7 @@ static inline int _loop(unsigned dry_run, u8 buf[],
unsigned lcnt0, lcnt1, ljmp0, ljmp1;
struct _arg_LPEND lpend;
- /* Max iterations possibile in DMALP is 256 */
+ /* Max iterations possible in DMALP is 256 */
if (*bursts >= 256*256) {
lcnt1 = 256;
lcnt0 = 256;
@@ -1446,7 +1446,7 @@ int pl330_update(const struct pl330_info *pi)
}
for (ev = 0; ev < pi->pcfg.num_events; ev++) {
- if (val & (1 << ev)) { /* Event occured */
+ if (val & (1 << ev)) { /* Event occurred */
struct pl330_thread *thrd;
u32 inten = readl(regs + INTEN);
int active;
diff --git a/arch/arm/include/asm/fpstate.h b/arch/arm/include/asm/fpstate.h
index ee5e03efc1b..3ad4c10d0d8 100644
--- a/arch/arm/include/asm/fpstate.h
+++ b/arch/arm/include/asm/fpstate.h
@@ -18,7 +18,7 @@
* VFP storage area has:
* - FPEXC, FPSCR, FPINST and FPINST2.
* - 16 or 32 double precision data registers
- * - an implementation-dependant word of state for FLDMX/FSTMX (pre-ARMv6)
+ * - an implementation-dependent word of state for FLDMX/FSTMX (pre-ARMv6)
*
* FPEXC will always be non-zero once the VFP has been used in this process.
*/
diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h
index c7afbc552c7..7e30874377e 100644
--- a/arch/arm/include/asm/glue-cache.h
+++ b/arch/arm/include/asm/glue-cache.h
@@ -126,7 +126,7 @@
#endif
#if !defined(_CACHE) && !defined(MULTI_CACHE)
-#error Unknown cache maintainence model
+#error Unknown cache maintenance model
#endif
#ifndef MULTI_CACHE
diff --git a/arch/arm/include/asm/glue.h b/arch/arm/include/asm/glue.h
index 0ec35d1698a..fbf71d75ec8 100644
--- a/arch/arm/include/asm/glue.h
+++ b/arch/arm/include/asm/glue.h
@@ -10,8 +10,8 @@
*
* This file provides the glue to stick the processor-specific bits
* into the kernel in an efficient manner. The idea is to use branches
- * when we're only targetting one class of TLB, or indirect calls
- * when we're targetting multiple classes of TLBs.
+ * when we're only targeting one class of TLB, or indirect calls
+ * when we're targeting multiple classes of TLBs.
*/
#ifdef __KERNEL__
diff --git a/arch/arm/include/asm/hardware/pl080.h b/arch/arm/include/asm/hardware/pl080.h
index f35b86e68dd..e4a04e4e562 100644
--- a/arch/arm/include/asm/hardware/pl080.h
+++ b/arch/arm/include/asm/hardware/pl080.h
@@ -16,7 +16,7 @@
* make it not entierly compatible with the PL080 specification from
* ARM. When in doubt, check the Samsung documentation first.
*
- * The Samsung defines are PL080S, and add an extra controll register,
+ * The Samsung defines are PL080S, and add an extra control register,
* the ability to move more than 2^11 counts of data and some extra
* OneNAND features.
*/
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 9a87823642d..885be097769 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -249,7 +249,7 @@ do { \
* cache totally. This means that the cache becomes inconsistent, and,
* since we use normal loads/stores as well, this is really bad.
* Typically, this causes oopsen in filp_close, but could have other,
- * more disasterous effects. There are two work-arounds:
+ * more disastrous effects. There are two work-arounds:
* 1. Disable interrupts and emulate the atomic swap
* 2. Clean the cache, perform atomic swap, flush the cache
*
diff --git a/arch/arm/include/asm/ucontext.h b/arch/arm/include/asm/ucontext.h
index 47f023aa849..14749aec94b 100644
--- a/arch/arm/include/asm/ucontext.h
+++ b/arch/arm/include/asm/ucontext.h
@@ -47,7 +47,7 @@ struct crunch_sigframe {
#endif
#ifdef CONFIG_IWMMXT
-/* iwmmxt_area is 0x98 bytes long, preceeded by 8 bytes of signature */
+/* iwmmxt_area is 0x98 bytes long, preceded by 8 bytes of signature */
#define IWMMXT_MAGIC 0x12ef842a
#define IWMMXT_STORAGE_SIZE (IWMMXT_SIZE + 8)
diff --git a/arch/arm/kernel/swp_emulate.c b/arch/arm/kernel/swp_emulate.c
index 7a576092291..40ee7e5045e 100644
--- a/arch/arm/kernel/swp_emulate.c
+++ b/arch/arm/kernel/swp_emulate.c
@@ -158,7 +158,7 @@ static int emulate_swpX(unsigned int address, unsigned int *data,
if (res == 0) {
/*
- * Barrier also required between aquiring a lock for a
+ * Barrier also required between acquiring a lock for a
* protected resource and accessing the resource. Inserted for
* same reason as above.
*/
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index 2e74a19874d..295e1e77fa6 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -76,7 +76,7 @@ static struct at91_udc_data __initdata carmeva_udc_data = {
.pullup_pin = AT91_PIN_PD9,
};
-/* FIXME: user dependant */
+/* FIXME: user dependent */
// static struct at91_cf_data __initdata carmeva_cf_data = {
// .det_pin = AT91_PIN_PB0,
// .rst_pin = AT91_PIN_PC5,
diff --git a/arch/arm/mach-at91/include/mach/at91_mci.h b/arch/arm/mach-at91/include/mach/at91_mci.h
index 27ac6f550fe..02182c16a02 100644
--- a/arch/arm/mach-at91/include/mach/at91_mci.h
+++ b/arch/arm/mach-at91/include/mach/at91_mci.h
@@ -102,7 +102,7 @@
#define AT91_MCI_RDIRE (1 << 17) /* Response Direction Error */
#define AT91_MCI_RCRCE (1 << 18) /* Response CRC Error */
#define AT91_MCI_RENDE (1 << 19) /* Response End Bit Error */
-#define AT91_MCI_RTOE (1 << 20) /* Reponse Time-out Error */
+#define AT91_MCI_RTOE (1 << 20) /* Response Time-out Error */
#define AT91_MCI_DCRCE (1 << 21) /* Data CRC Error */
#define AT91_MCI_DTOE (1 << 22) /* Data Time-out Error */
#define AT91_MCI_OVRE (1 << 30) /* Overrun */
diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
index ddeb6453675..056dc6674b6 100644
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -208,7 +208,7 @@ extern void at91_gpio_resume(void);
/*-------------------------------------------------------------------------*/
-/* wrappers for "new style" GPIO calls. the old AT91-specfic ones should
+/* wrappers for "new style" GPIO calls. the old AT91-specific ones should
* eventually be removed (along with this errno.h inclusion), and the
* gpio request/free calls should probably be implemented.
*/
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
index 77f84b40dda..a1f328357aa 100644
--- a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
+++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
@@ -551,7 +551,7 @@ int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig, /* [ IN ] Config
/****************************************************************************/
/**
-* @brief Check the existance of pending descriptor
+* @brief Check the existence of pending descriptor
*
* This function confirmes if there is any pending descriptor in the chain
* to program the channel
@@ -775,7 +775,7 @@ int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle, /* [ IN ] DMA Cha
/**
* @brief Read data DMAed to memory
*
-* This function will read data that has been DMAed to memory while transfering from:
+* This function will read data that has been DMAed to memory while transferring from:
* - Memory to memory
* - Peripheral to memory
*
@@ -941,7 +941,7 @@ int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configurat
/**
* @brief Sets channel specific user data
*
-* This function associates user data to a specif DMA channel
+* This function associates user data to a specific DMA channel
*
*/
/****************************************************************************/
diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c
index 8d1baf3f468..d87ad30dda3 100644
--- a/arch/arm/mach-bcmring/dma.c
+++ b/arch/arm/mach-bcmring/dma.c
@@ -629,7 +629,7 @@ EXPORT_SYMBOL(dma_get_device_descriptor_ring);
* Configures a DMA channel.
*
* @return
-* >= 0 - Initialization was successfull.
+* >= 0 - Initialization was successful.
*
* -EBUSY - Device is currently being used.
* -ENODEV - Device handed in is invalid.
@@ -673,7 +673,7 @@ static int ConfigChannel(DMA_Handle_t handle)
/**
* Initializes all of the data structures associated with the DMA.
* @return
-* >= 0 - Initialization was successfull.
+* >= 0 - Initialization was successful.
*
* -EBUSY - Device is currently being used.
* -ENODEV - Device handed in is invalid.
diff --git a/arch/arm/mach-bcmring/include/csp/dmacHw.h b/arch/arm/mach-bcmring/include/csp/dmacHw.h
index 6c8da2b9fc1..e6a1dc484ca 100644
--- a/arch/arm/mach-bcmring/include/csp/dmacHw.h
+++ b/arch/arm/mach-bcmring/include/csp/dmacHw.h
@@ -362,7 +362,7 @@ int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configurati
/**
* @brief Read data DMA transferred to memory
*
-* This function will read data that has been DMAed to memory while transfering from:
+* This function will read data that has been DMAed to memory while transferring from:
* - Memory to memory
* - Peripheral to memory
*
@@ -446,7 +446,7 @@ void dmacHw_stopTransfer(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle *
/****************************************************************************/
/**
-* @brief Check the existance of pending descriptor
+* @brief Check the existence of pending descriptor
*
* This function confirmes if there is any pending descriptor in the chain
* to program the channel
@@ -542,7 +542,7 @@ dmacHw_HANDLE_t dmacHw_getInterruptSource(void);
/**
* @brief Sets channel specific user data
*
-* This function associates user data to a specif DMA channel
+* This function associates user data to a specific DMA channel
*
*/
/****************************************************************************/
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
index 70eaea866cf..161973385fa 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
@@ -180,7 +180,7 @@ typedef enum {
#define chipcHw_XTAL_FREQ_Hz 25000000 /* Reference clock frequency in Hz */
-/* Programable pin defines */
+/* Programmable pin defines */
#define chipcHw_PIN_GPIO(n) ((((n) >= 0) && ((n) < (chipcHw_GPIO_COUNT))) ? (n) : 0xFFFFFFFF)
/* GPIO pin 0 - 60 */
#define chipcHw_PIN_UARTTXD (chipcHw_GPIO_COUNT + 0) /* UART Transmit */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
index c78833acb37..03238c29900 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
@@ -832,7 +832,7 @@ static inline void chipcHw_setUsbDevice(void)
/****************************************************************************/
/**
-* @brief Lower layer funtion to enable/disable a clock of a certain device
+* @brief Lower layer function to enable/disable a clock of a certain device
*
* This function enables/disables a core clock
*
diff --git a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
index e01fc4607c9..0aeb6a6fe7f 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
@@ -109,9 +109,9 @@
#define INTCHW_INTC0_DMA0C0 (1<<INTCHW_INTC0_DMA0C0_BITNUM)
/* INTC1 - interrupt controller 1 */
-#define INTCHW_INTC1_DDRVPMP_BITNUM 27 /* DDR and VPM PLL clock phase relationship interupt (Not for A0) */
+#define INTCHW_INTC1_DDRVPMP_BITNUM 27 /* DDR and VPM PLL clock phase relationship interrupt (Not for A0) */
#define INTCHW_INTC1_DDRVPMT_BITNUM 26 /* DDR and VPM HW phase align timeout interrupt (Not for A0) */
-#define INTCHW_INTC1_DDRP_BITNUM 26 /* DDR and PLL clock phase relationship interupt (For A0 only)) */
+#define INTCHW_INTC1_DDRP_BITNUM 26 /* DDR and PLL clock phase relationship interrupt (For A0 only)) */
#define INTCHW_INTC1_RTC2_BITNUM 25 /* Real time clock tamper interrupt */
#define INTCHW_INTC1_VDEC_BITNUM 24 /* Hantro Video Decoder interrupt */
/* Bits 13-23 are non-secure versions of the corresponding secure bits in SINTC bits 0-10. */
diff --git a/arch/arm/mach-bcmring/include/mach/reg_umi.h b/arch/arm/mach-bcmring/include/mach/reg_umi.h
index 06a355481ea..0992842caa7 100644
--- a/arch/arm/mach-bcmring/include/mach/reg_umi.h
+++ b/arch/arm/mach-bcmring/include/mach/reg_umi.h
@@ -88,7 +88,7 @@
/* REG_UMI_FLASH0/1/2_TCR, REG_UMI_SRAM0/1_TCR bits */
/* Enable wait pin during burst write or read */
#define REG_UMI_TCR_WAITEN 0x80000000
-/* Enable mem ctrlr to work iwth ext mem of lower freq than AHB clk */
+/* Enable mem ctrlr to work with ext mem of lower freq than AHB clk */
#define REG_UMI_TCR_LOWFREQ 0x40000000
/* 1=synch write, 0=async write */
#define REG_UMI_TCR_MEMTYPE_SYNCWRITE 0x20000000
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 6c389ff1020..3e7be2de96d 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -11,7 +11,7 @@
* DM644X-EVM board. It has:
* DM6446M02 module with 256MB NAND, 256MB RAM, TLV320AIC32 AIC,
* USB, Ethernet, SD/MMC, UART, THS8200, TVP7000 for video.
- * Additionaly realtime clock, IR remote control receiver,
+ * Additionally realtime clock, IR remote control receiver,
* IR Blaster based on MSP430 (firmware although is different
* from used in DM644X-EVM), internal ATA-6 3.5” HDD drive
* with PATA interface, two muxed red-green leds.
diff --git a/arch/arm/mach-davinci/cpufreq.c b/arch/arm/mach-davinci/cpufreq.c
index 4a68c2b1ec1..0a95be1512b 100644
--- a/arch/arm/mach-davinci/cpufreq.c
+++ b/arch/arm/mach-davinci/cpufreq.c
@@ -167,7 +167,7 @@ static int davinci_cpu_init(struct cpufreq_policy *policy)
/*
* Time measurement across the target() function yields ~1500-1800us
* time taken with no drivers on notification list.
- * Setting the latency to 2000 us to accomodate addition of drivers
+ * Setting the latency to 2000 us to accommodate addition of drivers
* to pre/post change notification list.
*/
policy->cpuinfo.transition_latency = 2000 * 1000;
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 68fe4c289d7..b95b9196dee 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1123,7 +1123,7 @@ void __init da850_init(void)
* This helps keeping the peripherals on this domain insulated
* from CPU frequency changes caused by DVFS. The firmware sets
* both PLL0 and PLL1 to the same frequency so, there should not
- * be any noticible change even in non-DVFS use cases.
+ * be any noticeable change even in non-DVFS use cases.
*/
da850_set_async3_src(1);
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 76364d1345d..f6801223964 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -314,7 +314,7 @@ static struct clk timer2_clk = {
.name = "timer2",
.parent = &pll1_aux_clk,
.lpsc = DAVINCI_LPSC_TIMER2,
- .usecount = 1, /* REVISIT: why cant' this be disabled? */
+ .usecount = 1, /* REVISIT: why can't' this be disabled? */
};
static struct clk timer3_clk = {
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 9a2376b3137..5f8a6542418 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -274,7 +274,7 @@ static struct clk timer2_clk = {
.name = "timer2",
.parent = &pll1_aux_clk,
.lpsc = DAVINCI_LPSC_TIMER2,
- .usecount = 1, /* REVISIT: why cant' this be disabled? */
+ .usecount = 1, /* REVISIT: why can't' this be disabled? */
};
static struct clk_lookup dm644x_clks[] = {
diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h
index cea6b897204..957fb87e832 100644
--- a/arch/arm/mach-davinci/include/mach/cputype.h
+++ b/arch/arm/mach-davinci/include/mach/cputype.h
@@ -4,7 +4,7 @@
* Author: Kevin Hilman, Deep Root Systems, LLC
*
* Defines the cpu_is_*() macros for runtime detection of DaVinci
- * device type. In addtion, if support for a given device is not
+ * device type. In addition, if support for a given device is not
* compiled in to the kernel, the macros return 0 so that
* resulting code can be optimized out.
*
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c
index 180b8a9d0d2..a5a9ff70b19 100644
--- a/arch/arm/mach-ep93xx/gpio.c
+++ b/arch/arm/mach-ep93xx/gpio.c
@@ -101,7 +101,7 @@ static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
{
/*
- * map discontiguous hw irq range to continous sw irq range:
+ * map discontiguous hw irq range to continuous sw irq range:
*
* IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
*/
diff --git a/arch/arm/mach-exynos4/include/mach/gpio.h b/arch/arm/mach-exynos4/include/mach/gpio.h
index 939728b38d4..be9266b10fd 100644
--- a/arch/arm/mach-exynos4/include/mach/gpio.h
+++ b/arch/arm/mach-exynos4/include/mach/gpio.h
@@ -18,7 +18,7 @@
#define gpio_cansleep __gpio_cansleep
#define gpio_to_irq __gpio_to_irq
-/* Practically, GPIO banks upto GPZ are the configurable gpio banks */
+/* Practically, GPIO banks up to GPZ are the configurable gpio banks */
/* GPIO bank sizes */
#define EXYNOS4_GPIO_A0_NR (8)
diff --git a/arch/arm/mach-exynos4/mct.c b/arch/arm/mach-exynos4/mct.c
index af82a8fbb68..14ac10b7ec0 100644
--- a/arch/arm/mach-exynos4/mct.c
+++ b/arch/arm/mach-exynos4/mct.c
@@ -276,7 +276,7 @@ static void exynos4_mct_tick_start(unsigned long cycles,
/* update interrupt count buffer */
exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
- /* enable MCT tick interupt */
+ /* enable MCT tick interrupt */
exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET);
diff --git a/arch/arm/mach-exynos4/setup-sdhci-gpio.c b/arch/arm/mach-exynos4/setup-sdhci-gpio.c
index 1b3d3a2de95..e8d08bf8965 100644
--- a/arch/arm/mach-exynos4/setup-sdhci-gpio.c
+++ b/arch/arm/mach-exynos4/setup-sdhci-gpio.c
@@ -38,14 +38,14 @@ void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
switch (width) {
case 8:
for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
- /* Data pin GPK1[3:6] to special-funtion 3 */
+ /* Data pin GPK1[3:6] to special-function 3 */
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
}
case 4:
for (gpio = EXYNOS4_GPK0(3); gpio <= EXYNOS4_GPK0(6); gpio++) {
- /* Data pin GPK0[3:6] to special-funtion 2 */
+ /* Data pin GPK0[3:6] to special-function 2 */
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
diff --git a/arch/arm/mach-exynos4/setup-sdhci.c b/arch/arm/mach-exynos4/setup-sdhci.c
index 85f9433d483..1e83f8cf236 100644
--- a/arch/arm/mach-exynos4/setup-sdhci.c
+++ b/arch/arm/mach-exynos4/setup-sdhci.c
@@ -35,7 +35,7 @@ void exynos4_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r,
{
u32 ctrl2, ctrl3;
- /* don't need to alter anything acording to card-type */
+ /* don't need to alter anything according to card-type */
ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index 773ea0c95b9..ba3dae352a2 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -225,7 +225,7 @@ static u32 iop13xx_atue_cfg_address(struct pci_bus *bus, int devfn, int where)
/* This routine checks the status of the last configuration cycle. If an error
* was detected it returns >0, else it returns a 0. The errors being checked
* are parity, master abort, target abort (master and target). These types of
- * errors occure during a config cycle where there is no device, like during
+ * errors occur during a config cycle where there is no device, like during
* the discovery stage.
*/
static int iop13xx_atux_pci_status(int clear)
@@ -332,7 +332,7 @@ static struct pci_ops iop13xx_atux_ops = {
/* This routine checks the status of the last configuration cycle. If an error
* was detected it returns >0, else it returns a 0. The errors being checked
* are parity, master abort, target abort (master and target). These types of
- * errors occure during a config cycle where there is no device, like during
+ * errors occur during a config cycle where there is no device, like during
* the discovery stage.
*/
static int iop13xx_atue_pci_status(int clear)
diff --git a/arch/arm/mach-kirkwood/tsx1x-common.c b/arch/arm/mach-kirkwood/tsx1x-common.c
index f781164e623..24294b2bc46 100644
--- a/arch/arm/mach-kirkwood/tsx1x-common.c
+++ b/arch/arm/mach-kirkwood/tsx1x-common.c
@@ -15,7 +15,7 @@
/****************************************************************************
* 16 MiB NOR flash. The struct mtd_partition is not in the same order as the
- * partitions on the device because we want to keep compatability with
+ * partitions on the device because we want to keep compatibility with
* the QNAP firmware.
* Layout as used by QNAP:
* 0x00000000-0x00080000 : "U-Boot"
diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c
index e76d41bb705..b9c80597b7b 100644
--- a/arch/arm/mach-lpc32xx/pm.c
+++ b/arch/arm/mach-lpc32xx/pm.c
@@ -41,7 +41,7 @@
* DRAM clocking and refresh are slightly different for systems with DDR
* DRAM or regular SDRAM devices. If SDRAM is used in the system, the
* SDRAM will still be accessible in direct-run mode. In DDR based systems,
- * a transistion to direct-run mode will stop all DDR accesses (no clocks).
+ * a transition to direct-run mode will stop all DDR accesses (no clocks).
* Because of this, the code to switch power modes and the code to enter
* and exit DRAM self-refresh modes must not be executed in DRAM. A small
* section of IRAM is used instead for this.
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c
index aeb9ae23e6c..99833b9485c 100644
--- a/arch/arm/mach-mmp/time.c
+++ b/arch/arm/mach-mmp/time.c
@@ -9,7 +9,7 @@
* 2008-04-11: Jason Chagas <Jason.chagas@marvell.com>
* 2008-10-08: Bin Yang <bin.yang@marvell.com>
*
- * The timers module actually includes three timers, each timer with upto
+ * The timers module actually includes three timers, each timer with up to
* three match comparators. Timer #0 is used here in free-running mode as
* the clock source, and match comparator #1 used as clock event device.
*
diff --git a/arch/arm/mach-msm/acpuclock-arm11.c b/arch/arm/mach-msm/acpuclock-arm11.c
index 7ffbd987eb5..805d4ee53f7 100644
--- a/arch/arm/mach-msm/acpuclock-arm11.c
+++ b/arch/arm/mach-msm/acpuclock-arm11.c
@@ -343,7 +343,7 @@ int acpuclk_set_rate(unsigned long rate, int for_power_collapse)
}
}
- /* Set wait states for CPU inbetween frequency changes */
+ /* Set wait states for CPU between frequency changes */
reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
reg_clkctl |= (100 << 16); /* set WT_ST_CNT */
writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
diff --git a/arch/arm/mach-msm/scm.c b/arch/arm/mach-msm/scm.c
index cfa808dd489..232f97a0450 100644
--- a/arch/arm/mach-msm/scm.c
+++ b/arch/arm/mach-msm/scm.c
@@ -46,7 +46,7 @@ static DEFINE_MUTEX(scm_lock);
* @id: command to be executed
* @buf: buffer returned from scm_get_command_buffer()
*
- * An SCM command is layed out in memory as follows:
+ * An SCM command is laid out in memory as follows:
*
* ------------------- <--- struct scm_command
* | command header |
diff --git a/arch/arm/mach-omap1/ams-delta-fiq-handler.S b/arch/arm/mach-omap1/ams-delta-fiq-handler.S
index 927d5a18176..c1c5fb6a5b4 100644
--- a/arch/arm/mach-omap1/ams-delta-fiq-handler.S
+++ b/arch/arm/mach-omap1/ams-delta-fiq-handler.S
@@ -79,7 +79,7 @@
/*
- * Register useage
+ * Register usage
* r8 - temporary
* r9 - the driver buffer
* r10 - temporary
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index d41fe2d0616..0ad781db4e6 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -399,7 +399,7 @@ static void __init omap_sx1_init(void)
sx1_mmc_init();
/* turn on USB power */
- /* sx1_setusbpower(1); cant do it here because i2c is not ready */
+ /* sx1_setusbpower(1); can't do it here because i2c is not ready */
gpio_request(1, "A_IRDA_OFF");
gpio_request(11, "A_SWITCH");
gpio_request(15, "A_USB_ON");
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index b0f4c231595..36f26c3fa25 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -281,7 +281,7 @@ static inline void omap_init_audio(void) {}
* Claiming GPIOs, and setting their direction and initial values, is the
* responsibility of the device drivers. So is responding to probe().
*
- * Board-specific knowlege like creating devices or pin setup is to be
+ * Board-specific knowledge like creating devices or pin setup is to be
* kept out of drivers as much as possible. In particular, pin setup
* may be handled by the boot loader, and drivers should expect it will
* normally have been done by the time they're probed.
diff --git a/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h b/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h
index 7a2df29400c..23eed0035ed 100644
--- a/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h
+++ b/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h
@@ -31,7 +31,7 @@
#endif
/*
- * These are the offsets from the begining of the fiq_buffer. They are put here
+ * These are the offsets from the beginning of the fiq_buffer. They are put here
* since the buffer and header need to be accessed by drivers servicing devices
* which generate GPIO interrupts - e.g. keyboard, modem, hook switch.
*/
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 5f8a2fd0633..34cf982b967 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -696,7 +696,7 @@ static void __init igep2_init(void)
igep2_init_smsc911x();
/*
- * WLAN-BT combo module from MuRata wich has a Marvell WLAN
+ * WLAN-BT combo module from MuRata which has a Marvell WLAN
* (88W8686) + CSR Bluetooth chipset. Uses SDIO interface.
*/
igep2_wlan_bt_init();
diff --git a/arch/arm/mach-omap2/board-igep0030.c b/arch/arm/mach-omap2/board-igep0030.c
index b10db0e6ee6..2cf86c3cb1a 100644
--- a/arch/arm/mach-omap2/board-igep0030.c
+++ b/arch/arm/mach-omap2/board-igep0030.c
@@ -440,7 +440,7 @@ static void __init igep3_init(void)
igep3_leds_init();
/*
- * WLAN-BT combo module from MuRata wich has a Marvell WLAN
+ * WLAN-BT combo module from MuRata which has a Marvell WLAN
* (88W8686) + CSR Bluetooth chipset. Uses SDIO interface.
*/
igep3_wifi_bt_init();
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index ab878545bd9..6cb6c03293d 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -258,7 +258,7 @@ static void _resolve_clkdm_deps(struct clockdomain *clkdm,
* clkdm_init - set up the clockdomain layer
* @clkdms: optional pointer to an array of clockdomains to register
* @init_autodeps: optional pointer to an array of autodeps to register
- * @custom_funcs: func pointers for arch specfic implementations
+ * @custom_funcs: func pointers for arch specific implementations
*
* Set up internal state. If a pointer to an array of clockdomains
* @clkdms was supplied, loop through the list of clockdomains,
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 85b3dce6564..5823584d9cd 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -125,7 +125,7 @@ struct clockdomain {
};
/**
- * struct clkdm_ops - Arch specfic function implementations
+ * struct clkdm_ops - Arch specific function implementations
* @clkdm_add_wkdep: Add a wakeup dependency between clk domains
* @clkdm_del_wkdep: Delete a wakeup dependency between clk domains
* @clkdm_read_wkdep: Read wakeup dependency state between clk domains
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index a44c5230340..1c240eff391 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -297,8 +297,8 @@ DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
/**
* omap3_cpuidle_update_states() - Update the cpuidle states
- * @mpu_deepest_state: Enable states upto and including this for mpu domain
- * @core_deepest_state: Enable states upto and including this for core domain
+ * @mpu_deepest_state: Enable states up to and including this for mpu domain
+ * @core_deepest_state: Enable states up to and including this for core domain
*
* This goes through the list of states available and enables and disables the
* validity of C states based on deepest state that can be achieved for the
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 84d1b735fe8..7b855856459 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -253,7 +253,7 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data
ARRAY_SIZE(omap_keyboard_latency), 0);
if (IS_ERR(od)) {
- WARN(1, "Cant build omap_device for %s:%s.\n",
+ WARN(1, "Can't build omap_device for %s:%s.\n",
name, oh->name);
return PTR_ERR(od);
}
@@ -373,7 +373,7 @@ static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
od = omap_device_build(name, spi_num, oh, pdata,
sizeof(*pdata), omap_mcspi_latency,
ARRAY_SIZE(omap_mcspi_latency), 0);
- WARN(IS_ERR(od), "Cant build omap_device for %s:%s\n",
+ WARN(IS_ERR(od), "Can't build omap_device for %s:%s\n",
name, oh->name);
kfree(pdata);
return 0;
@@ -725,7 +725,7 @@ static int __init omap_init_wdt(void)
od = omap_device_build(dev_name, id, oh, NULL, 0,
omap_wdt_latency,
ARRAY_SIZE(omap_wdt_latency), 0);
- WARN(IS_ERR(od), "Cant build omap_device for %s:%s.\n",
+ WARN(IS_ERR(od), "Can't build omap_device for %s:%s.\n",
dev_name, oh->name);
return 0;
}
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index 34922b2d2e3..c9ff0e79703 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -262,7 +262,7 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
omap2_dma_latency, ARRAY_SIZE(omap2_dma_latency), 0);
kfree(p);
if (IS_ERR(od)) {
- pr_err("%s: Cant build omap_device for %s:%s.\n",
+ pr_err("%s: Can't build omap_device for %s:%s.\n",
__func__, name, oh->name);
return PTR_ERR(od);
}
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 413de18c1d2..9529842ae05 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -82,7 +82,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
kfree(pdata);
if (IS_ERR(od)) {
- WARN(1, "Cant build omap_device for %s:%s.\n",
+ WARN(1, "Can't build omap_device for %s:%s.\n",
name, oh->name);
return PTR_ERR(od);
}
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 137e1a5f3d8..b2f30bed5a2 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -465,7 +465,7 @@ void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
od = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
sizeof(struct omap_mmc_platform_data), ohl, ohl_cnt, false);
if (IS_ERR(od)) {
- WARN(1, "Cant build omap_device for %s:%s.\n", name, oh->name);
+ WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name);
kfree(mmc_data->slots[0].name);
goto done;
}
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 565b9064a32..4a6ef6ab845 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -149,7 +149,7 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
ARRAY_SIZE(omap2_mcbsp_latency), false);
kfree(pdata);
if (IS_ERR(od)) {
- pr_err("%s: Cant build omap_device for %s:%s.\n", __func__,
+ pr_err("%s: Can't build omap_device for %s:%s.\n", __func__,
name, oh->name);
return PTR_ERR(od);
}
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index bb043cbb388..a4ab1e36431 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -518,7 +518,7 @@ static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
seq_printf(s, "/* %s */\n", m->muxnames[mode]);
/*
- * XXX: Might be revisited to support differences accross
+ * XXX: Might be revisited to support differences across
* same OMAP generation.
*/
seq_printf(s, "OMAP%d_MUX(%s, ", omap_gen, m0_def);
diff --git a/arch/arm/mach-omap2/mux2430.h b/arch/arm/mach-omap2/mux2430.h
index adbea0d03e0..9fd93149ebd 100644
--- a/arch/arm/mach-omap2/mux2430.h
+++ b/arch/arm/mach-omap2/mux2430.h
@@ -22,7 +22,7 @@
* absolute addresses. The name in the macro is the mode-0 name of
* the pin. NOTE: These registers are 8-bits wide.
*
- * Note that these defines use SDMMC instead of MMC for compability
+ * Note that these defines use SDMMC instead of MMC for compatibility
* with signal names used in 3630.
*/
#define OMAP2430_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x000
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index a860fb5024c..e6e3810db77 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -1559,7 +1559,7 @@ static struct omap_hwmod omap2430_i2c1_hwmod = {
* I2CHS IP's do not follow the usual pattern.
* prcm_reg_id alone cannot be used to program
* the iclk and fclk. Needs to be handled using
- * additonal flags when clk handling is moved
+ * additional flags when clk handling is moved
* to hwmod framework.
*/
.module_offs = CORE_MOD,
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index e2e605fe913..05f6abc96b0 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -112,12 +112,12 @@ int omap4430_phy_power(struct device *dev, int ID, int on)
else
/*
* Enable VBUS Valid, AValid and IDDIG
- * high impedence
+ * high impedance
*/
__raw_writel(IDDIG | AVALID | VBUSVALID,
ctrl_base + USBOTGHS_CONTROL);
} else {
- /* Enable session END and IDIG to high impedence. */
+ /* Enable session END and IDIG to high impedance. */
__raw_writel(SESSEND | IDDIG, ctrl_base +
USBOTGHS_CONTROL);
}
diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
index 0a8e74e3e81..07d6140baa9 100644
--- a/arch/arm/mach-omap2/omap_twl.c
+++ b/arch/arm/mach-omap2/omap_twl.c
@@ -308,7 +308,7 @@ int __init omap3_twl_init(void)
* Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages,
* in those scenarios this bit is to be cleared (enable = false).
*
- * Returns 0 on sucess, error is returned if I2C read/write fails.
+ * Returns 0 on success, error is returned if I2C read/write fails.
*/
int __init omap3_twl_set_sr_bit(bool enable)
{
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 49c6513e90d..9af08473bf1 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -196,7 +196,7 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused)
/**
* pwrdm_init - set up the powerdomain layer
* @pwrdm_list: array of struct powerdomain pointers to register
- * @custom_funcs: func pointers for arch specfic implementations
+ * @custom_funcs: func pointers for arch specific implementations
*
* Loop through the array of powerdomains @pwrdm_list, registering all
* that are available on the current CPU. If pwrdm_list is supplied
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 027f40bd235..d23d979b9c3 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -121,7 +121,7 @@ struct powerdomain {
};
/**
- * struct pwrdm_ops - Arch specfic function implementations
+ * struct pwrdm_ops - Arch specific function implementations
* @pwrdm_set_next_pwrst: Set the target power state for a pd
* @pwrdm_read_next_pwrst: Read the target power state set for a pd
* @pwrdm_read_pwrst: Read the current power state of a pd
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index 9c9c113788b..469a920a74d 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -72,7 +72,7 @@ static struct powerdomain mpu_3xxx_pwrdm = {
/*
* The USBTLL Save-and-Restore mechanism is broken on
- * 3430s upto ES3.0 and 3630ES1.0. Hence this feature
+ * 3430s up to ES3.0 and 3630ES1.0. Hence this feature
* needs to be disabled on these chips.
* Refer: 3430 errata ID i459 and 3630 errata ID i579
*
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 8f674c9442b..13e24f913dd 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -247,7 +247,7 @@ static void sr_stop_vddautocomp(struct omap_sr *sr)
* driver register and sr device intializtion API's. Only one call
* will ultimately succeed.
*
- * Currenly this function registers interrrupt handler for a particular SR
+ * Currently this function registers interrrupt handler for a particular SR
* if smartreflex class driver is already registered and has
* requested for interrupts and the SR interrupt line in present.
*/
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index c6facf7becf..6fb520999b6 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -851,7 +851,7 @@ int omap_voltage_scale_vdd(struct voltagedomain *voltdm,
* @voltdm: pointer to the VDD whose voltage is to be reset.
*
* This API finds out the correct voltage the voltage domain is supposed
- * to be at and resets the voltage to that level. Should be used expecially
+ * to be at and resets the voltage to that level. Should be used especially
* while disabling any voltage compensation modules.
*/
void omap_voltage_reset(struct voltagedomain *voltdm)
@@ -912,7 +912,7 @@ void omap_voltage_get_volttable(struct voltagedomain *voltdm,
* This API searches only through the non-compensated voltages int the
* voltage table.
* Returns pointer to the voltage table entry corresponding to volt on
- * sucess. Returns -ENODATA if no voltage table exisits for the passed voltage
+ * success. Returns -ENODATA if no voltage table exisits for the passed voltage
* domain or if there is no matching entry.
*/
struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index 1a5d6a0e260..5ceafdccc45 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -19,7 +19,7 @@
#include "common.h"
/*
- * The Orion has fully programable address map. There's a separate address
+ * The Orion has fully programmable address map. There's a separate address
* map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIe, USB,
* Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own
* address decode windows that allow it to access any of the Orion resources.
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
index 429ecafe9fd..a5930f83958 100644
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -190,7 +190,7 @@ err_free_1:
* The power front LEDs (blue and red) and SATA red LEDs are controlled via a
* single GPIO line and are compatible with the leds-gpio driver.
*
- * The SATA blue LEDs have some hardware blink capabilities which are detailled
+ * The SATA blue LEDs have some hardware blink capabilities which are detailed
* in the following array:
*
* SATAx blue LED | SATAx activity | LED state
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index f0f43e13ac8..e6d64494d3d 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -36,7 +36,7 @@
/****************************************************************************
* 8MiB NOR flash. The struct mtd_partition is not in the same order as the
- * partitions on the device because we want to keep compatability with
+ * partitions on the device because we want to keep compatibility with
* existing QNAP firmware.
*
* Layout as used by QNAP:
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index 92f393f08fa..9eac8192d92 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -56,7 +56,7 @@
/****************************************************************************
* 8MiB NOR flash. The struct mtd_partition is not in the same order as the
- * partitions on the device because we want to keep compatability with
+ * partitions on the device because we want to keep compatibility with
* existing QNAP firmware.
*
* Layout as used by QNAP:
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
index e4fb4668c26..207ecb49a61 100644
--- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
@@ -38,7 +38,7 @@
#define PCMD(x) __REG(0x40F50110 + ((x) << 2))
/*
- * Slave Power Managment Unit
+ * Slave Power Management Unit
*/
#define ASCR __REG(0x40f40000) /* Application Subsystem Power Status/Configuration */
#define ARSR __REG(0x40f40004) /* Application Subsystem Reset Status */
diff --git a/arch/arm/mach-pxa/include/mach/zeus.h b/arch/arm/mach-pxa/include/mach/zeus.h
index faa408ab7ad..0641f31a56b 100644
--- a/arch/arm/mach-pxa/include/mach/zeus.h
+++ b/arch/arm/mach-pxa/include/mach/zeus.h
@@ -64,7 +64,7 @@
/*
* CPLD registers:
- * Only 4 registers, but spreaded over a 32MB address space.
+ * Only 4 registers, but spread over a 32MB address space.
* Be gentle, and remap that over 32kB...
*/
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index dd13bb63259..23925db8ff7 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -458,7 +458,7 @@ static struct platform_device strataflash = {
/*
* Suspend/Resume bootstrap management
*
- * MIO A701 reboot sequence is highly ROM dependant. From the one dissassembled,
+ * MIO A701 reboot sequence is highly ROM dependent. From the one dissassembled,
* this sequence is as follows :
* - disables interrupts
* - initialize SDRAM (self refresh RAM into active RAM)
diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h
index cf68136cc66..b2b2a5bb275 100644
--- a/arch/arm/mach-s3c2410/include/mach/dma.h
+++ b/arch/arm/mach-s3c2410/include/mach/dma.h
@@ -19,7 +19,7 @@
#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
/* We use `virtual` dma channels to hide the fact we have only a limited
- * number of DMA channels, and not of all of them (dependant on the device)
+ * number of DMA channels, and not of all of them (dependent on the device)
* can be attached to any DMA source. We therefore let the DMA core handle
* the allocation of hardware channels to clients.
*/
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-mem.h
index 7f7c5294796..988a6863e54 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-mem.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-mem.h
@@ -101,7 +101,7 @@
#define S3C2410_BANKCON_PMC16 (0x03)
/* bank configurations for banks 0..7, note banks
- * 6 and 7 have differnt configurations depending on
+ * 6 and 7 have different configurations depending on
* the memory type bits */
#define S3C2410_BANKCON_Tacp2 (0x0 << 2)
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 66f44440d5d..079dcaa602d 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -252,7 +252,7 @@ static struct s3c24xx_led_platdata n30_blue_led_pdata = {
.def_trigger = "",
};
-/* This is the blue LED on the device. Originaly used to indicate GPS activity
+/* This is the blue LED on the device. Originally used to indicate GPS activity
* by flashing. */
static struct s3c24xx_led_platdata n35_blue_led_pdata = {
.name = "blue_led",
diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c
index dfedc9c9e00..dd3120df09f 100644
--- a/arch/arm/mach-s3c2440/mach-mini2440.c
+++ b/arch/arm/mach-s3c2440/mach-mini2440.c
@@ -155,7 +155,7 @@ static struct s3c2410fb_display mini2440_lcd_cfg[] __initdata = {
* the same timings, however, anything smaller than 1024x768
* will only be displayed in the top left corner of a 1024x768
* XGA output unless you add optional dip switches to the shield.
- * Therefore timings for other resolutions have been ommited here.
+ * Therefore timings for other resolutions have been omitted here.
*/
[2] = {
_LCD_DECLARE(
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c
index c35585cf8c4..b197171e7d0 100644
--- a/arch/arm/mach-s3c64xx/dma.c
+++ b/arch/arm/mach-s3c64xx/dma.c
@@ -315,7 +315,7 @@ int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op)
case S3C2410_DMAOP_FLUSH:
return s3c64xx_dma_flush(chan);
- /* belive PAUSE/RESUME are no-ops */
+ /* believe PAUSE/RESUME are no-ops */
case S3C2410_DMAOP_PAUSE:
case S3C2410_DMAOP_RESUME:
case S3C2410_DMAOP_STARTED:
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-fb.h b/arch/arm/mach-s5pc100/include/mach/regs-fb.h
index 4be4cc9abf7..07aa4d6054f 100644
--- a/arch/arm/mach-s5pc100/include/mach/regs-fb.h
+++ b/arch/arm/mach-s5pc100/include/mach/regs-fb.h
@@ -29,7 +29,7 @@
#define WPALCON_H (0x19c)
#define WPALCON_L (0x1a0)
-/* Pallete contro for WPAL0 and WPAL1 is the same as in S3C64xx, but
+/* Palette control for WPAL0 and WPAL1 is the same as in S3C64xx, but
* different for WPAL2-4
*/
/* In WPALCON_L (aka WPALCON) */
diff --git a/arch/arm/mach-s5pc100/setup-sdhci.c b/arch/arm/mach-s5pc100/setup-sdhci.c
index f16946e456e..be25879bb2e 100644
--- a/arch/arm/mach-s5pc100/setup-sdhci.c
+++ b/arch/arm/mach-s5pc100/setup-sdhci.c
@@ -40,7 +40,7 @@ void s5pc100_setup_sdhci0_cfg_card(struct platform_device *dev,
{
u32 ctrl2, ctrl3;
- /* don't need to alter anything acording to card-type */
+ /* don't need to alter anything according to card-type */
writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
diff --git a/arch/arm/mach-s5pv210/include/mach/gpio.h b/arch/arm/mach-s5pv210/include/mach/gpio.h
index 1f4b595534c..a5a1e331f8e 100644
--- a/arch/arm/mach-s5pv210/include/mach/gpio.h
+++ b/arch/arm/mach-s5pv210/include/mach/gpio.h
@@ -18,7 +18,7 @@
#define gpio_cansleep __gpio_cansleep
#define gpio_to_irq __gpio_to_irq
-/* Practically, GPIO banks upto MP03 are the configurable gpio banks */
+/* Practically, GPIO banks up to MP03 are the configurable gpio banks */
/* GPIO bank sizes */
#define S5PV210_GPIO_A0_NR (8)
diff --git a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
index 746777d56df..3e3ac05bb7b 100644
--- a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
+++ b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
@@ -32,10 +32,10 @@ void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
switch (width) {
case 8:
- /* GPG1[3:6] special-funtion 3 */
+ /* GPG1[3:6] special-function 3 */
s3c_gpio_cfgrange_nopull(S5PV210_GPG1(3), 4, S3C_GPIO_SFN(3));
case 4:
- /* GPG0[3:6] special-funtion 2 */
+ /* GPG0[3:6] special-function 2 */
s3c_gpio_cfgrange_nopull(S5PV210_GPG0(3), 4, S3C_GPIO_SFN(2));
default:
break;
diff --git a/arch/arm/mach-s5pv210/setup-sdhci.c b/arch/arm/mach-s5pv210/setup-sdhci.c
index c32e202731c..a83b6c909f6 100644
--- a/arch/arm/mach-s5pv210/setup-sdhci.c
+++ b/arch/arm/mach-s5pv210/setup-sdhci.c
@@ -38,7 +38,7 @@ void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev,
{
u32 ctrl2, ctrl3;
- /* don't need to alter anything acording to card-type */
+ /* don't need to alter anything according to card-type */
writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile
index e697691eed2..41252d22e65 100644
--- a/arch/arm/mach-sa1100/Makefile
+++ b/arch/arm/mach-sa1100/Makefile
@@ -50,7 +50,7 @@ led-$(CONFIG_SA1100_SIMPAD) += leds-simpad.o
# LEDs support
obj-$(CONFIG_LEDS) += $(led-y)
-# Miscelaneous functions
+# Miscellaneous functions
obj-$(CONFIG_PM) += pm.o sleep.o
obj-$(CONFIG_SA1100_SSP) += ssp.o
diff --git a/arch/arm/mach-sa1100/cpu-sa1100.c b/arch/arm/mach-sa1100/cpu-sa1100.c
index 07d4e8ba371..aaa8acf76b7 100644
--- a/arch/arm/mach-sa1100/cpu-sa1100.c
+++ b/arch/arm/mach-sa1100/cpu-sa1100.c
@@ -68,7 +68,7 @@
* clock change in ROM and jump to that code from the kernel. The main
* disadvantage is that the ROM has to be modified, which is not
* possible on all SA-1100 platforms. Another disadvantage is that
- * jumping to ROM makes clock switching unecessary complicated.
+ * jumping to ROM makes clock switching unnecessary complicated.
*
* The idea behind this driver is that the memory configuration can be
* changed while running from DRAM (even with interrupts turned on!)
diff --git a/arch/arm/mach-sa1100/include/mach/SA-1100.h b/arch/arm/mach-sa1100/include/mach/SA-1100.h
index 4f7ea012e1e..bae8296f5db 100644
--- a/arch/arm/mach-sa1100/include/mach/SA-1100.h
+++ b/arch/arm/mach-sa1100/include/mach/SA-1100.h
@@ -1794,7 +1794,7 @@
(DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
DDAR_Ser4SSPRc + DDAR_DevAdd (__PREG(Ser4SSDR)))
-#define DCSR_RUN 0x00000001 /* DMA RUNing */
+#define DCSR_RUN 0x00000001 /* DMA running */
#define DCSR_IE 0x00000002 /* DMA Interrupt Enable */
#define DCSR_ERROR 0x00000004 /* DMA ERROR */
#define DCSR_DONEA 0x00000008 /* DONE DMA transfer buffer A */
diff --git a/arch/arm/mach-sa1100/jornada720_ssp.c b/arch/arm/mach-sa1100/jornada720_ssp.c
index 9d490c66891..f50b00bd18a 100644
--- a/arch/arm/mach-sa1100/jornada720_ssp.c
+++ b/arch/arm/mach-sa1100/jornada720_ssp.c
@@ -29,7 +29,7 @@ static unsigned long jornada_ssp_flags;
/**
* jornada_ssp_reverse - reverses input byte
*
- * we need to reverse all data we recieve from the mcu due to its physical location
+ * we need to reverse all data we receive from the mcu due to its physical location
* returns : 01110111 -> 11101110
*/
u8 inline jornada_ssp_reverse(u8 byte)
@@ -179,7 +179,7 @@ static int __devinit jornada_ssp_probe(struct platform_device *dev)
static int jornada_ssp_remove(struct platform_device *dev)
{
- /* Note that this doesnt actually remove the driver, since theres nothing to remove
+ /* Note that this doesn't actually remove the driver, since theres nothing to remove
* It just makes sure everything is turned off */
GPSR = GPIO_GPIO25;
ssp_exit();
diff --git a/arch/arm/mach-tegra/dma.c b/arch/arm/mach-tegra/dma.c
index e945ae28ee7..f4ef5eb317b 100644
--- a/arch/arm/mach-tegra/dma.c
+++ b/arch/arm/mach-tegra/dma.c
@@ -223,7 +223,7 @@ int tegra_dma_dequeue_req(struct tegra_dma_channel *ch,
* - Change the source selector to invalid to stop the DMA from
* FIFO to memory.
* - Read the status register to know the number of pending
- * bytes to be transfered.
+ * bytes to be transferred.
* - Finally stop or program the DMA to the next buffer in the
* list.
*/
@@ -244,7 +244,7 @@ int tegra_dma_dequeue_req(struct tegra_dma_channel *ch,
if (status & STA_BUSY)
req->bytes_transferred -= to_transfer;
- /* In continous transfer mode, DMA only tracks the count of the
+ /* In continuous transfer mode, DMA only tracks the count of the
* half DMA buffer. So, if the DMA already finished half the DMA
* then add the half buffer to the completed count.
*
diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h
index 39011bd9a92..d0132e8031a 100644
--- a/arch/arm/mach-tegra/include/mach/dma.h
+++ b/arch/arm/mach-tegra/include/mach/dma.h
@@ -92,11 +92,11 @@ struct tegra_dma_req {
/* This is a called from the DMA ISR context when the DMA is still in
* progress and is actively filling same buffer.
*
- * In case of continous mode receive, this threshold is 1/2 the buffer
+ * In case of continuous mode receive, this threshold is 1/2 the buffer
* size. In other cases, this will not even be called as there is no
* hardware support for it.
*
- * In the case of continous mode receive, if there is next req already
+ * In the case of continuous mode receive, if there is next req already
* queued, DMA programs the HW to use that req when this req is
* completed. If there is no "next req" queued, then DMA ISR doesn't do
* anything before calling this callback.
diff --git a/arch/arm/mach-u300/clock.c b/arch/arm/mach-u300/clock.c
index fabcc49abe8..5535dd0a78c 100644
--- a/arch/arm/mach-u300/clock.c
+++ b/arch/arm/mach-u300/clock.c
@@ -263,7 +263,7 @@ static void disable_i2s0_vcxo(void)
val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
val &= ~U300_SYSCON_CCR_I2S0_USE_VCXO;
writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
- /* Deactivate VCXO if noone else is using VCXO */
+ /* Deactivate VCXO if no one else is using VCXO */
if (!(val & U300_SYSCON_CCR_I2S1_USE_VCXO))
val &= ~U300_SYSCON_CCR_TURN_VCXO_ON;
writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
@@ -283,7 +283,7 @@ static void disable_i2s1_vcxo(void)
val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
val &= ~U300_SYSCON_CCR_I2S1_USE_VCXO;
writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
- /* Deactivate VCXO if noone else is using VCXO */
+ /* Deactivate VCXO if no one else is using VCXO */
if (!(val & U300_SYSCON_CCR_I2S0_USE_VCXO))
val &= ~U300_SYSCON_CCR_TURN_VCXO_ON;
writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
@@ -649,7 +649,7 @@ static unsigned long clk_round_rate_cpuclk(struct clk *clk, unsigned long rate)
*/
long clk_round_rate(struct clk *clk, unsigned long rate)
{
- /* TODO: get apropriate switches for EMIFCLK, AHBCLK and MCLK */
+ /* TODO: get appropriate switches for EMIFCLK, AHBCLK and MCLK */
/* Else default to fixed value */
if (clk->round_rate) {
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index dc8746d7826..af913741e6e 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -52,7 +52,7 @@ static struct ab8500_gpio_platform_data ab8500_gpio_pdata = {
* on value present in GpioSel1 to GpioSel6 and AlternatFunction
* register. This is the array of 7 configuration settings.
* One has to compile time decide these settings. Below is the
- * explaination of these setting
+ * explanation of these setting
* GpioSel1 = 0x00 => Pins GPIO1 to GPIO8 are not used as GPIO
* GpioSel2 = 0x1E => Pins GPIO10 to GPIO13 are configured as GPIO
* GpioSel3 = 0x80 => Pin GPIO24 is configured as GPIO
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h
index 0fefb34c11e..16647b25537 100644
--- a/arch/arm/mach-ux500/include/mach/db8500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h
@@ -58,7 +58,7 @@
#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000)
#define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000)
-/* per7 base addressess */
+/* per7 base addresses */
#define U8500_CR_BASE_ED (U8500_PER7_BASE_ED + 0x8000)
#define U8500_MTU0_BASE_ED (U8500_PER7_BASE_ED + 0xa000)
#define U8500_MTU1_BASE_ED (U8500_PER7_BASE_ED + 0xb000)
@@ -68,7 +68,7 @@
#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
-/* per6 base addressess */
+/* per6 base addresses */
#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000)
#define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000)
#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000)
@@ -79,11 +79,11 @@
#define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000)
#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000)
-/* per5 base addressess */
+/* per5 base addresses */
#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000)
#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000)
-/* per4 base addressess */
+/* per4 base addresses */
#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x00000)
#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x01000)
#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x02000)
@@ -106,7 +106,7 @@
#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000)
#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000)
-/* per2 base addressess */
+/* per2 base addresses */
#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000)
#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000)
#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000)
diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S
index d3644db467b..f40c69656d8 100644
--- a/arch/arm/mm/cache-v4wb.S
+++ b/arch/arm/mm/cache-v4wb.S
@@ -32,7 +32,7 @@
/*
* This is the size at which it becomes more efficient to
* clean the whole cache, rather than using the individual
- * cache line maintainence instructions.
+ * cache line maintenance instructions.
*
* Size Clean (ticks) Dirty (ticks)
* 4096 21 20 21 53 55 54
diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S
index 49c2b66cf3d..a7b276dbda1 100644
--- a/arch/arm/mm/cache-v4wt.S
+++ b/arch/arm/mm/cache-v4wt.S
@@ -34,7 +34,7 @@
/*
* This is the size at which it becomes more efficient to
* clean the whole cache, rather than using the individual
- * cache line maintainence instructions.
+ * cache line maintenance instructions.
*
* *** This needs benchmarking
*/
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 6136e68ce95..dc18d81ef8c 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -96,7 +96,7 @@ ENDPROC(v7_flush_dcache_all)
* Flush the entire cache system.
* The data cache flush is now achieved using atomic clean / invalidates
* working outwards from L1 cache. This is done using Set/Way based cache
- * maintainance instructions.
+ * maintenance instructions.
* The instruction cache can still be invalidated back to the point of
* unification in a single instruction.
*
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 226e3d8351c..6c4e7fd6c8a 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -64,7 +64,7 @@
/*
* This is the size at which it becomes more efficient to
* clean the whole cache, rather than using the individual
- * cache line maintainence instructions.
+ * cache line maintenance instructions.
*/
#define CACHE_DLIMIT 32768
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 86d9c2cf0bc..4ce947c1962 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -64,7 +64,7 @@
/*
* This is the size at which it becomes more efficient to
* clean the whole cache, rather than using the individual
- * cache line maintainence instructions.
+ * cache line maintenance instructions.
*/
#define CACHE_DLIMIT 32768
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 83d3dd34f84..c8884c5413a 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -53,7 +53,7 @@
/*
* This is the size at which it becomes more efficient to
* clean the whole cache, rather than using the individual
- * cache line maintainence instructions.
+ * cache line maintenance instructions.
*/
#define CACHE_DLIMIT 32768
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 686043ee728..413684660aa 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -53,7 +53,7 @@
/*
* This is the size at which it becomes more efficient to
* clean the whole cache, rather than using the individual
- * cache line maintainence instructions.
+ * cache line maintenance instructions.
*/
#define CACHE_DLIMIT 32768
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index 665266da143..7a06e5964f5 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -63,7 +63,7 @@ ENTRY(cpu_arm720_proc_fin)
/*
* Function: arm720_proc_do_idle(void)
* Params : r0 = unused
- * Purpose : put the processer in proper idle mode
+ * Purpose : put the processor in proper idle mode
*/
ENTRY(cpu_arm720_do_idle)
mov pc, lr
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 219980ec8b6..b46eb21f05c 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -53,7 +53,7 @@
/*
* This is the size at which it becomes more efficient to
* clean the whole cache, rather than using the individual
- * cache line maintainence instructions.
+ * cache line maintenance instructions.
*/
#define CACHE_DLIMIT 65536
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 36154b1e792..95ba1fc56e4 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -54,7 +54,7 @@
/*
* This is the size at which it becomes more efficient to
* clean the whole cache, rather than using the individual
- * cache line maintainence instructions. (I think this should
+ * cache line maintenance instructions. (I think this should
* be 32768).
*/
#define CACHE_DLIMIT 8192
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 89c5e0009c4..541e4774eea 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -77,7 +77,7 @@
/*
* This is the size at which it becomes more efficient to
* clean the whole cache, rather than using the individual
- * cache line maintainence instructions.
+ * cache line maintenance instructions.
*/
#define CACHE_DLIMIT 8192
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index e32fa499194..34261f9486b 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -85,7 +85,7 @@
/*
* Sanity check the PTE configuration for the code below - which makes
- * certain assumptions about how these bits are layed out.
+ * certain assumptions about how these bits are laid out.
*/
#ifdef CONFIG_MMU
#if L_PTE_SHARED != PTE_EXT_SHARED
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 832b6bdc192..bfa0c9f611c 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -132,7 +132,7 @@ ENTRY(cpu_v6_do_suspend)
mrc p15, 0, r6, c3, c0, 0 @ Domain ID
mrc p15, 0, r7, c2, c0, 0 @ Translation table base 0
mrc p15, 0, r8, c2, c0, 1 @ Translation table base 1
- mrc p15, 0, r9, c1, c0, 1 @ auxillary control register
+ mrc p15, 0, r9, c1, c0, 1 @ auxiliary control register
mrc p15, 0, r10, c1, c0, 2 @ co-processor access control
mrc p15, 0, r11, c1, c0, 0 @ control register
stmia r0, {r4 - r11}
@@ -151,7 +151,7 @@ ENTRY(cpu_v6_do_resume)
mcr p15, 0, r6, c3, c0, 0 @ Domain ID
mcr p15, 0, r7, c2, c0, 0 @ Translation table base 0
mcr p15, 0, r8, c2, c0, 1 @ Translation table base 1
- mcr p15, 0, r9, c1, c0, 1 @ auxillary control register
+ mcr p15, 0, r9, c1, c0, 1 @ auxiliary control register
mcr p15, 0, r10, c1, c0, 2 @ co-processor access control
mcr p15, 0, ip, c2, c0, 2 @ TTB control register
mcr p15, 0, ip, c7, c5, 4 @ ISB
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 262fa88a743..c35618e42f6 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -237,7 +237,7 @@ ENTRY(cpu_v7_do_resume)
mcr p15, 0, r7, c2, c0, 0 @ TTB 0
mcr p15, 0, r8, c2, c0, 1 @ TTB 1
mcr p15, 0, ip, c2, c0, 2 @ TTB control register
- mcr p15, 0, r10, c1, c0, 1 @ Auxillary control register
+ mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register
mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control
ldr r4, =PRRR @ PRRR
ldr r5, =NMRR @ NMRR
diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c
index ce81481becf..4268a2bdf14 100644
--- a/arch/arm/plat-mxc/cpufreq.c
+++ b/arch/arm/plat-mxc/cpufreq.c
@@ -13,7 +13,7 @@
/*
* A driver for the Freescale Semiconductor i.MXC CPUfreq module.
- * The CPUFREQ driver is for controling CPU frequency. It allows you to change
+ * The CPUFREQ driver is for controlling CPU frequency. It allows you to change
* the CPU clock speed on the fly.
*/
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
index bd9bb979914..2e49e71b1b9 100644
--- a/arch/arm/plat-mxc/include/mach/entry-macro.S
+++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
@@ -33,9 +33,9 @@
.macro arch_ret_to_user, tmp1, tmp2
.endm
- @ this macro checks which interrupt occured
+ @ this macro checks which interrupt occurred
@ and returns its number in irqnr
- @ and returns if an interrupt occured in irqstat
+ @ and returns if an interrupt occurred in irqstat
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
#ifndef CONFIG_MXC_TZIC
@ Load offset & priority of the highest priority
diff --git a/arch/arm/plat-mxc/include/mach/mxc_nand.h b/arch/arm/plat-mxc/include/mach/mxc_nand.h
index 04c0d060d81..6bb96ef1600 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_nand.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_nand.h
@@ -24,7 +24,7 @@
struct mxc_nand_platform_data {
unsigned int width; /* data bus width in bytes */
- unsigned int hw_ecc:1; /* 0 if supress hardware ECC */
+ unsigned int hw_ecc:1; /* 0 if suppress hardware ECC */
unsigned int flash_bbt:1; /* set to 1 to use a flash based bbt */
struct mtd_partition *parts; /* partition table */
int nr_parts; /* size of parts */
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 7d9f815cede..ea28f98d5d6 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -280,7 +280,7 @@ EXPORT_SYMBOL(omap_dsp_get_mempool_base);
* Claiming GPIOs, and setting their direction and initial values, is the
* responsibility of the device drivers. So is responding to probe().
*
- * Board-specific knowlege like creating devices or pin setup is to be
+ * Board-specific knowledge like creating devices or pin setup is to be
* kept out of drivers as much as possible. In particular, pin setup
* may be handled by the boot loader, and drivers should expect it will
* normally have been done by the time they're probed.
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 2ec3b5d9f21..c22217c2ee5 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -1019,7 +1019,7 @@ EXPORT_SYMBOL(omap_set_dma_callback);
* If the channel is running the caller must disable interrupts prior calling
* this function and process the returned value before re-enabling interrupt to
* prevent races with the interrupt handler. Note that in continuous mode there
- * is a chance for CSSA_L register overflow inbetween the two reads resulting
+ * is a chance for CSSA_L register overflow between the two reads resulting
* in incorrect return value.
*/
dma_addr_t omap_get_dma_src_pos(int lch)
@@ -1046,7 +1046,7 @@ EXPORT_SYMBOL(omap_get_dma_src_pos);
* If the channel is running the caller must disable interrupts prior calling
* this function and process the returned value before re-enabling interrupt to
* prevent races with the interrupt handler. Note that in continuous mode there
- * is a chance for CDSA_L register overflow inbetween the two reads resulting
+ * is a chance for CDSA_L register overflow between the two reads resulting
* in incorrect return value.
*/
dma_addr_t omap_get_dma_dst_pos(int lch)
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index d6f9fa0f62a..cac2e8ac696 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -93,7 +93,7 @@ extern void omap_gpio_restore_context(void);
/* Wrappers for "new style" GPIO calls, using the new infrastructure
* which lets us plug in FPGA, I2C, and other implementations.
* *
- * The original OMAP-specfic calls should eventually be removed.
+ * The original OMAP-specific calls should eventually be removed.
*/
#include <linux/errno.h>
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index 12b31616503..1527929b445 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -90,7 +90,7 @@ enum omap_ecc {
/* 1-bit ecc: stored at end of spare area */
OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */
OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */
- /* 1-bit ecc: stored at begining of spare area as romcode */
+ /* 1-bit ecc: stored at beginning of spare area as romcode */
OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method & romcode layout */
};
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index d598d9fd65a..5587acf0eb2 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -1103,7 +1103,7 @@ int omap_mcbsp_pollread(unsigned int id, u16 *buf)
/* resend */
return -1;
} else {
- /* wait for recieve confirmation */
+ /* wait for receive confirmation */
int attemps = 0;
while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) {
if (attemps++ > 1000) {
diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-pxa/include/plat/mfp.h
index 75f65647124..89e68e07b0a 100644
--- a/arch/arm/plat-pxa/include/plat/mfp.h
+++ b/arch/arm/plat-pxa/include/plat/mfp.h
@@ -434,7 +434,7 @@ typedef unsigned long mfp_cfg_t;
*
* mfp_init_addr() - accepts a table of "mfp_addr_map" structure, which
* represents a range of MFP pins from "start" to "end", with the offset
- * begining at "offset", to define a single pin, let "end" = -1.
+ * beginning at "offset", to define a single pin, let "end" = -1.
*
* use
*
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index c2064c30871..0291bd6e236 100644
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -23,7 +23,7 @@ obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o
obj-$(CONFIG_CPU_FREQ_S3C24XX) += cpu-freq.o
obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpu-freq-debugfs.o
-# Architecture dependant builds
+# Architecture dependent builds
obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o
obj-$(CONFIG_PM) += pm.o
diff --git a/arch/arm/plat-s3c24xx/cpu-freq.c b/arch/arm/plat-s3c24xx/cpu-freq.c
index eea75ff81d1..b3d3d027899 100644
--- a/arch/arm/plat-s3c24xx/cpu-freq.c
+++ b/arch/arm/plat-s3c24xx/cpu-freq.c
@@ -455,7 +455,7 @@ static int s3c_cpufreq_resume(struct cpufreq_policy *policy)
/* whilst we will be called later on, we try and re-set the
* cpu frequencies as soon as possible so that we do not end
- * up resuming devices and then immediatley having to re-set
+ * up resuming devices and then immediately having to re-set
* a number of settings once these devices have restarted.
*
* as a note, it is expected devices are not used until they
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index 6ad274e7593..27ea852e337 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -557,7 +557,7 @@ s3c2410_dma_lastxfer(struct s3c2410_dma_chan *chan)
break;
case S3C2410_DMALOAD_1LOADED_1RUNNING:
- /* I belive in this case we do not have anything to do
+ /* I believe in this case we do not have anything to do
* until the next buffer comes along, and we turn off the
* reload */
return;
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
index 46dd078147d..cd6d67c8382 100644
--- a/arch/arm/plat-s5p/irq-gpioint.c
+++ b/arch/arm/plat-s5p/irq-gpioint.c
@@ -208,7 +208,7 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
}
/*
- * chained GPIO irq has been sucessfully registered, allocate new gpio
+ * chained GPIO irq has been successfully registered, allocate new gpio
* int group and assign irq nubmers
*/
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
index 9a82b887491..983c578b827 100644
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -21,7 +21,7 @@ struct clk;
* @set_parent: set the clock's parent, see clk_set_parent().
*
* Group the common clock implementations together so that we
- * don't have to keep setting the same fiels again. We leave
+ * don't have to keep setting the same fields again. We leave
* enable in struct clk.
*
* Adding an extra layer of indirection into the process should
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
index 5603db0b79b..3ad8386599c 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
@@ -114,7 +114,7 @@ extern unsigned s3c_gpio_getcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
* of control per GPIO, generally in the form of:
* 0000 = Input
* 0001 = Output
- * others = Special functions (dependant on bank)
+ * others = Special functions (dependent on bank)
*
* Note, since the code to deal with the case where there are two control
* registers instead of one, we do not have a separate set of functions for
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
index 5e04fa6eda7..1762dcb4cb9 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
@@ -125,7 +125,7 @@ extern int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
*
* These values control the state of the weak pull-{up,down} resistors
* available on most pins on the S3C series. Not all chips support both
- * up or down settings, and it may be dependant on the chip that is being
+ * up or down settings, and it may be dependent on the chip that is being
* used to whether the particular mode is available.
*/
#define S3C_GPIO_PULL_NONE ((__force s3c_gpio_pull_t)0x00)
@@ -138,7 +138,7 @@ extern int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
* @pull: The configuration for the pull resistor.
*
* This function sets the state of the pull-{up,down} resistor for the
- * specified pin. It will return 0 if successfull, or a negative error
+ * specified pin. It will return 0 if successful, or a negative error
* code if the pin cannot support the requested pull setting.
*
* @pull is one of S3C_GPIO_PULL_NONE, S3C_GPIO_PULL_DOWN or S3C_GPIO_PULL_UP.
@@ -202,7 +202,7 @@ extern s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin);
* @drvstr: The new value of the driver strength
*
* This function sets the driver strength value for the specified pin.
- * It will return 0 if successfull, or a negative error code if the pin
+ * It will return 0 if successful, or a negative error code if the pin
* cannot support the requested setting.
*/
extern int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr);
diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h
index dac35d0a711..8cad4cf19c3 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-core.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-core.h
@@ -108,7 +108,7 @@ extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip);
* of control per GPIO, generally in the form of:
* 0000 = Input
* 0001 = Output
- * others = Special functions (dependant on bank)
+ * others = Special functions (dependent on bank)
*
* Note, since the code to deal with the case where there are two control
* registers instead of one, we do not have a separate set of function
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index b0bdf16549d..058e09654fe 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -57,7 +57,7 @@ enum clk_types {
* @cfg_gpio: Configure the GPIO for a specific card bit-width
* @cfg_card: Configure the interface for a specific card and speed. This
* is necessary the controllers and/or GPIO blocks require the
- * changing of driver-strength and other controls dependant on
+ * changing of driver-strength and other controls dependent on
* the card and speed of operation.
*
* Initialisation data specific to either the machine or the platform
@@ -108,7 +108,7 @@ extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata;
extern struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata;
extern struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata;
-/* Helper function availablity */
+/* Helper function availability */
extern void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
extern void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
diff --git a/arch/arm/plat-samsung/s3c-pl330.c b/arch/arm/plat-samsung/s3c-pl330.c
index b4ff8d74ac4..f85638c6f5a 100644
--- a/arch/arm/plat-samsung/s3c-pl330.c
+++ b/arch/arm/plat-samsung/s3c-pl330.c
@@ -68,7 +68,7 @@ struct s3c_pl330_xfer {
* @req: Two requests to communicate with the PL330 engine.
* @callback_fn: Callback function to the client.
* @rqcfg: Channel configuration for the xfers.
- * @xfer_head: Pointer to the xfer to be next excecuted.
+ * @xfer_head: Pointer to the xfer to be next executed.
* @dmac: Pointer to the DMAC that manages this channel, NULL if the
* channel is available to be acquired.
* @client: Client of this channel. NULL if the
diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h
index 2ae6606930a..fcc0d0ad4a1 100644
--- a/arch/arm/plat-spear/include/plat/clock.h
+++ b/arch/arm/plat-spear/include/plat/clock.h
@@ -89,7 +89,7 @@ struct rate_config {
* @sibling: node for list of clocks having same parents
* @private_data: clock specific private data
* @node: list to maintain clocks linearly
- * @cl: clocklook up assoicated with this clock
+ * @cl: clocklook up associated with this clock
* @dent: object for debugfs
*/
struct clk {