path: root/arch/arm/mm
diff options
authorNicolas Pitre <nicolas.pitre@linaro.org>2012-11-08 19:46:07 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2012-11-13 11:47:41 +0000
commite40678559fdf3f56ce9a349365fbf39e1f63ecc0 (patch)
treebf17297c143e5aa6f55f73bd44d703a4f3817686 /arch/arm/mm
parentb62655f4c6f3e4d21934eee14ac2ac5cd479c97c (diff)
ARM: 7573/1: idmap: use flush_cache_louis() and flush TLBs only when necessary
Flushing the cache is needed for the hardware to see the idmap table and therefore can be done at init time. On ARMv7 it is not necessary to flush L2 so flush_cache_louis() is used here instead. There is no point flushing the cache in setup_mm_for_reboot() as the caller should, and already is, taking care of this. If switching the memory map requires a cache flush, then cpu_switch_mm() already includes that operation. What is not done by cpu_switch_mm() on ASID capable CPUs is TLB flushing as the whole point of the ASID is to tag the TLBs and avoid flushing them on a context switch. Since we don't have a clean ASID for the identity mapping, we need to flush the TLB explicitly in that case. Otherwise this is already performed by cpu_switch_mm(). Signed-off-by: Nicolas Pitre <nico@linaro.org> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm')
1 files changed, 10 insertions, 4 deletions
diff --git a/arch/arm/mm/idmap.c b/arch/arm/mm/idmap.c
index ab88ed4f8e0..99db769307e 100644
--- a/arch/arm/mm/idmap.c
+++ b/arch/arm/mm/idmap.c
@@ -92,6 +92,9 @@ static int __init init_static_idmap(void)
(long long)idmap_start, (long long)idmap_end);
identity_mapping_add(idmap_pgd, idmap_start, idmap_end);
+ /* Flush L1 for the hardware to see this page table content */
+ flush_cache_louis();
return 0;
@@ -103,12 +106,15 @@ early_initcall(init_static_idmap);
void setup_mm_for_reboot(void)
- /* Clean and invalidate L1. */
- flush_cache_all();
/* Switch to the identity mapping. */
cpu_switch_mm(idmap_pgd, &init_mm);
- /* Flush the TLB. */
+ /*
+ * We don't have a clean ASID for the identity mapping, which
+ * may clash with virtual addresses of the previous page tables
+ * and therefore potentially in the TLB.
+ */