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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2006-12-13 14:34:43 +0000
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-12-13 14:34:43 +0000
commitad1ae2fe7fe68414ef29eab3c87b48841f8b72f2 (patch)
treef23fc22424f874c1295318904b273c08d00654ab /arch/arm/mm/proc-v6.S
parentf06b97ffd1ed7a96d5022d52f795fba8483afb75 (diff)
[ARM] Unuse another Linux PTE bit
L_PTE_ASID is not really required to be stored in every PTE, since we can identify it via the address passed to set_pte_at(). So, create set_pte_ext() which takes the address of the PTE to set, the Linux PTE value, and the additional CPU PTE bits which aren't encoded in the Linux PTE value. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-v6.S')
-rw-r--r--arch/arm/mm/proc-v6.S30
1 files changed, 16 insertions, 14 deletions
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 513c6c28256..7b1843befb9 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -103,13 +103,14 @@ ENTRY(cpu_v6_switch_mm)
mov pc, lr
/*
- * cpu_v6_set_pte(ptep, pte)
+ * cpu_v6_set_pte_ext(ptep, pte, ext)
*
* Set a level 2 translation table entry.
*
* - ptep - pointer to level 2 translation table entry
* (hardware version is stored at -1024 bytes)
* - pte - PTE value to store
+ * - ext - value for extended PTE bits
*
* Permissions:
* YUWD APX AP1 AP0 SVC User
@@ -121,33 +122,34 @@ ENTRY(cpu_v6_switch_mm)
* 11x0 0 1 0 r/w r/o
* 1111 0 1 1 r/w r/w
*/
-ENTRY(cpu_v6_set_pte)
+ENTRY(cpu_v6_set_pte_ext)
#ifdef CONFIG_MMU
str r1, [r0], #-2048 @ linux version
- bic r2, r1, #0x000003f0
- bic r2, r2, #0x00000003
- orr r2, r2, #PTE_EXT_AP0 | 2
+ bic r3, r1, #0x000003f0
+ bic r3, r3, #0x00000003
+ orr r3, r3, r2
+ orr r3, r3, #PTE_EXT_AP0 | 2
tst r1, #L_PTE_WRITE
tstne r1, #L_PTE_DIRTY
- orreq r2, r2, #PTE_EXT_APX
+ orreq r3, r3, #PTE_EXT_APX
tst r1, #L_PTE_USER
- orrne r2, r2, #PTE_EXT_AP1
- tstne r2, #PTE_EXT_APX
- bicne r2, r2, #PTE_EXT_APX | PTE_EXT_AP0
+ orrne r3, r3, #PTE_EXT_AP1
+ tstne r3, #PTE_EXT_APX
+ bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
tst r1, #L_PTE_YOUNG
- biceq r2, r2, #PTE_EXT_APX | PTE_EXT_AP_MASK
+ biceq r3, r3, #PTE_EXT_APX | PTE_EXT_AP_MASK
tst r1, #L_PTE_EXEC
- orreq r2, r2, #PTE_EXT_XN
+ orreq r3, r3, #PTE_EXT_XN
tst r1, #L_PTE_PRESENT
- moveq r2, #0
+ moveq r3, #0
- str r2, [r0]
+ str r3, [r0]
mcr p15, 0, r0, c7, c10, 1 @ flush_pte
#endif
mov pc, lr
@@ -233,7 +235,7 @@ ENTRY(v6_processor_functions)
.word cpu_v6_do_idle
.word cpu_v6_dcache_clean_area
.word cpu_v6_switch_mm
- .word cpu_v6_set_pte
+ .word cpu_v6_set_pte_ext
.size v6_processor_functions, . - v6_processor_functions
.type cpu_arch_name, #object