path: root/arch/arm/mm/proc-v6.S
diff options
authorRussell King <rmk@dyn-67.arm.linux.org.uk>2006-06-29 15:09:57 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-06-29 15:09:57 +0100
commit22b1908610dd7ff68471cd4fbd383dbdfe5e0ecd (patch)
tree696d910ef791433a6a6bbd30ae841a106ce78a88 /arch/arm/mm/proc-v6.S
parent264edb35ce5c85749bfdd2942c74b786ea1cde41 (diff)
[ARM] nommu: provide a way for correct control register value selection
Most MMU-based CPUs have a restriction on the setting of the data cache enable and mmu enable bits in the control register, whereby if the data cache is enabled, the MMU must also be enabled. Enabling the data cache without the MMU is an invalid combination. However, there are CPUs where the data cache can be enabled without the MMU. In order to allow these CPUs to take advantage of that, provide a method whereby each proc-*.S file defines the control regsiter value for use with nommu (with the MMU disabled.) Later on, when we add support for enabling the MMU on these devices, we can adjust the "crval" macro to also enable the data cache for nommu. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-v6.S')
1 files changed, 6 insertions, 9 deletions
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index ca13d4d05f6..f0075f1b1fc 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -212,11 +212,11 @@ __v6_setup:
orr r0, r0, #(0xf << 20)
mcr p15, 0, r0, c1, c0, 2 @ Enable full access to VFP
+ adr r5, v6_crval
+ ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0, 0 @ read control register
- ldr r5, v6_cr1_clear @ get mask for bits to clear
bic r0, r0, r5 @ clear bits them
- ldr r5, v6_cr1_set @ get mask for bits to set
- orr r0, r0, r5 @ set them
+ orr r0, r0, r6 @ set them
mov pc, lr @ return to head.S:__ret
@@ -225,12 +225,9 @@ __v6_setup:
* rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
* 0 110 0011 1.00 .111 1101 < we want
- .type v6_cr1_clear, #object
- .type v6_cr1_set, #object
- .word 0x01e0fb7f
- .word 0x00c0387d
+ .type v6_crval, #object
+ crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
.type v6_processor_functions, #object