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authorHyok S. Choi <hyok.choi@samsung.com>2006-06-28 14:10:01 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-06-28 17:59:56 +0100
commitd090dddaba7c8da6401bb259340dce05ca32f564 (patch)
treec35d9e22dc09d40144b4a672962269ff60c9ad07 /arch/arm/mm/proc-arm720.S
parenta4f7e76367f7775ecf534a37b4623c83d9d7ba74 (diff)
[ARM] nommu: Initial uCLinux support for MMU-based CPUs
In noMMU mode, various of functions which are defined in mm/proc-*.S is not valid or needed to be avoided. i.g. switch_mm is not needed, just returns and this makes the I & D caches are valid which shows great improvement of performance including task switching and IPC. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-arm720.S')
-rw-r--r--arch/arm/mm/proc-arm720.S12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index 26f00ee2ad9..86102467d37 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -4,6 +4,7 @@
* Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
* Rob Scott (rscott@mtrob.fdns.net)
* Copyright (C) 2000 ARM Limited, Deep Blue Solutions Ltd.
+ * hacked for non-paged-MM by Hyok S. Choi, 2004.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -29,6 +30,7 @@
* out of 'proc-arm6,7.S' per RMK discussion
* 07-25-2000 SJH Added idle function.
* 08-25-2000 DBS Updated for integration of ARM Ltd version.
+ * 04-20-2004 HSC modified for non-paged memory management mode.
*/
#include <linux/linkage.h>
#include <linux/init.h>
@@ -75,10 +77,12 @@ ENTRY(cpu_arm720_do_idle)
* the new.
*/
ENTRY(cpu_arm720_switch_mm)
+#ifdef CONFIG_MMU
mov r1, #0
mcr p15, 0, r1, c7, c7, 0 @ invalidate cache
mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
+#endif
mov pc, lr
/*
@@ -89,6 +93,7 @@ ENTRY(cpu_arm720_switch_mm)
*/
.align 5
ENTRY(cpu_arm720_set_pte)
+#ifdef CONFIG_MMU
str r1, [r0], #-2048 @ linux version
eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -107,6 +112,7 @@ ENTRY(cpu_arm720_set_pte)
movne r2, #0
str r2, [r0] @ hardware version
+#endif
mov pc, lr
/*
@@ -117,7 +123,9 @@ ENTRY(cpu_arm720_set_pte)
ENTRY(cpu_arm720_reset)
mov ip, #0
mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
+#ifdef CONFIG_MMU
mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
+#endif
mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
bic ip, ip, #0x000f @ ............wcam
bic ip, ip, #0x2100 @ ..v....s........
@@ -130,7 +138,9 @@ ENTRY(cpu_arm720_reset)
__arm710_setup:
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
+#ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
+#endif
mrc p15, 0, r0, c1, c0 @ get control register
ldr r5, arm710_cr1_clear
bic r0, r0, r5
@@ -156,7 +166,9 @@ arm710_cr1_set:
__arm720_setup:
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
+#ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
+#endif
mrc p15, 0, r0, c1, c0 @ get control register
ldr r5, arm720_cr1_clear
bic r0, r0, r5