path: root/arch/arm/mm/proc-arm720.S
diff options
authorRussell King <rmk+kernel@arm.linux.org.uk>2010-07-26 12:22:12 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-07-27 10:48:42 +0100
commit9ca03a21e320a6bf44559323527aba704bcc8772 (patch)
treec3422c49decfdca220c0088938546c49ee71ba64 /arch/arm/mm/proc-arm720.S
parentb8ab5397bcbd92e3fd4a9770e0bf59315fa38dab (diff)
ARM: Factor out common code from cpu_proc_fin()
All implementations of cpu_proc_fin() start by disabling interrupts and then flush caches. Rather than have every processors proc_fin() implementation do this, move it out into generic code - and move the cache flush past setup_mm_for_reboot() (so it can benefit from having caches still enabled.) This allows cpu_proc_fin() to become independent of the L1/L2 cache types, and eventually move the L2 cache flushing into the L2 support code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-arm720.S')
1 files changed, 1 insertions, 5 deletions
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index 0b62de24466..9d96824134f 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -54,15 +54,11 @@ ENTRY(cpu_arm720_proc_init)
mov pc, lr
- stmfd sp!, {lr}
- mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
- msr cpsr_c, ip
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x1000 @ ...i............
bic r0, r0, #0x000e @ ............wca.
mcr p15, 0, r0, c1, c0, 0 @ disable caches
- mcr p15, 0, r1, c7, c7, 0 @ invalidate cache
- ldmfd sp!, {pc}
+ mov pc, lr
* Function: arm720_proc_do_idle(void)