path: root/arch/arm/mm/proc-arm720.S
diff options
authorRussell King <rmk@dyn-67.arm.linux.org.uk>2006-06-29 15:09:57 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-06-29 15:09:57 +0100
commit22b1908610dd7ff68471cd4fbd383dbdfe5e0ecd (patch)
tree696d910ef791433a6a6bbd30ae841a106ce78a88 /arch/arm/mm/proc-arm720.S
parent264edb35ce5c85749bfdd2942c74b786ea1cde41 (diff)
[ARM] nommu: provide a way for correct control register value selection
Most MMU-based CPUs have a restriction on the setting of the data cache enable and mmu enable bits in the control register, whereby if the data cache is enabled, the MMU must also be enabled. Enabling the data cache without the MMU is an invalid combination. However, there are CPUs where the data cache can be enabled without the MMU. In order to allow these CPUs to take advantage of that, provide a method whereby each proc-*.S file defines the control regsiter value for use with nommu (with the MMU disabled.) Later on, when we add support for enabling the MMU on these devices, we can adjust the "crval" macro to also enable the data cache for nommu. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-arm720.S')
1 files changed, 6 insertions, 9 deletions
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index 86102467d37..b22bc3af232 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -169,11 +169,11 @@ __arm720_setup:
mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
+ adr r5, arm720_crval
+ ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0 @ get control register
- ldr r5, arm720_cr1_clear
bic r0, r0, r5
- ldr r5, arm720_cr1_set
- orr r0, r0, r5
+ orr r0, r0, r6
mov pc, lr @ __ret (head.S)
.size __arm720_setup, . - __arm720_setup
@@ -183,12 +183,9 @@ __arm720_setup:
* ..1. 1001 ..11 1101
- .type arm720_cr1_clear, #object
- .type arm720_cr1_set, #object
- .word 0x2f3f
- .word 0x213d
+ .type arm720_crval, #object
+ crval clear=0x00002f3f, mmuset=0x0000213d, ucset=0x00000130