path: root/arch/arm/mm/cache-v7.S
diff options
authorCatalin Marinas <catalin.marinas@arm.com>2010-05-07 18:03:05 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-05-08 10:44:30 +0100
commitb8349b569aae661dea9d59d7d2ee587ccea3336c (patch)
tree297ce3147521e0658321d61114a045bef4eca1d0 /arch/arm/mm/cache-v7.S
parentf4d6477f7f073b99220386d62f5bf54bec3482cc (diff)
ARM: 6112/1: Use the Inner Shareable I-cache and BTB ops on ARMv7 SMP
The standard I-cache Invalidate All (ICIALLU) and Branch Predication Invalidate All (BPIALL) operations are not automatically broadcast to the other CPUs in an ARMv7 MP system. The patch adds the Inner Shareable variants, ICIALLUIS and BPIALLIS, if ARMv7 and SMP. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/cache-v7.S')
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index bcd64f26587..06a90dcfc60 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -167,7 +167,11 @@ ENTRY(v7_coherent_user_range)
cmp r0, r1
blo 1b
mov r0, #0
+#ifdef CONFIG_SMP
+ mcr p15, 0, r0, c7, c1, 6 @ invalidate BTB Inner Shareable
mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
mov pc, lr