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authorHuang Shijie <b32955@freescale.com>2012-09-10 15:17:56 +0800
committerShawn Guo <shawn.guo@linaro.org>2012-09-19 13:30:03 +0800
commitcc7887c3b1a08d3900160d93df4ddda5fa7f725b (patch)
treecdc0ae18258ecfee8228a16a03644cb9f54e6a1e /arch/arm/mach-imx/clk-imx6q.c
parent97a53092a148e6c70aabf13835143cc3dd4b524c (diff)
ARM: imx6q: use pll2_pfd2_396m as the enfc_sel's parent
The gpmi-nand driver can support the ONFI nand chip's EDO (extra data out) mode in the asynchrounous mode. In the asynchrounous mode 5, the gpmi needs 100MHz clock for the IO. But with the pll2_pfd0_352m, we can not get the 100MHz clock. So choose pll2_pfd2_396m as enfc_sel's parent. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/mach-imx/clk-imx6q.c')
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index bbc71f57b92..744327fc5e2 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -404,6 +404,13 @@ int __init mx6q_clocks_init(void)
clk_register_clkdev(clk[ahb], "ahb", NULL);
clk_register_clkdev(clk[cko1], "cko1", NULL);
+ /*
+ * The gpmi needs 100MHz frequency in the EDO/Sync mode,
+ * We can not get the 100MHz from the pll2_pfd0_352m.
+ * So choose pll2_pfd2_396m as enfc_sel's parent.
+ */
+ clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]);
+
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
clk_prepare_enable(clk[clks_init_on[i]]);