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authorAlexander Shiyan <shc_work@mail.ru>2012-08-21 20:59:33 +0400
committerArnd Bergmann <arnd@arndb.de>2012-09-28 21:14:07 +0200
commitafc49177b412dfe547c60740ac1f1db7f805da43 (patch)
tree76f6d587823cdf92236eccd4a184fa6233075172 /arch/arm/mach-clps711x
parent7255f87a7169689be2d4722375744a1f932d4b28 (diff)
ARM: clps711x: Fix register definitions
This patch contain some fixes: - Fixes the address of register PORTE. - Corrects name for DAIDR0 register. - Removes unused definition for SYNCIO_CFGLEN. - Fixes definition SYNCIO_FRMLEN. Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Diffstat (limited to 'arch/arm/mach-clps711x')
-rw-r--r--arch/arm/mach-clps711x/include/mach/clps711x.h9
1 files changed, 4 insertions, 5 deletions
diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h
index 1dd806f2847..c82e21ca49c 100644
--- a/arch/arm/mach-clps711x/include/mach/clps711x.h
+++ b/arch/arm/mach-clps711x/include/mach/clps711x.h
@@ -31,8 +31,8 @@
#define PBDDR (0x0041)
#define PCDDR (0x0042)
#define PDDDR (0x0043)
-#define PEDR (0x0080)
-#define PEDDR (0x00c0)
+#define PEDR (0x0083)
+#define PEDDR (0x00c3)
#define SYSCON1 (0x0100)
#define SYSFLG1 (0x0140)
#define MEMCFG1 (0x0180)
@@ -77,7 +77,7 @@
#define KBDEOI (0x1700)
#define DAIR (0x2000)
-#define DAIR0 (0x2040)
+#define DAIDR0 (0x2040)
#define DAIDR1 (0x2080)
#define DAIDR2 (0x20c0)
#define DAISR (0x2100)
@@ -191,8 +191,7 @@
#define UBRLCR_WRDLEN8 (3 << 17)
#define UBRLCR_WRDLEN_MASK (3 << 17)
-#define SYNCIO_FRMLEN(x) (((x) & 0x3f) << 7)
-#define SYNCIO_CFGLEN(x) ((x) & 0x7f)
+#define SYNCIO_FRMLEN(x) (((x) & 0x1f) << 8)
#define SYNCIO_SMCKEN (1 << 13)
#define SYNCIO_TXFRMEN (1 << 14)