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authorAlexander Shiyan <shc_work@mail.ru>2012-05-13 02:40:57 +0400
committerArnd Bergmann <arnd@arndb.de>2012-05-13 21:53:03 +0200
commit94bd32792e905ae25f63491f06d7d3018b350dd2 (patch)
tree354e3637ab09679d1a31feceb640cf095bc11332 /arch/arm/mach-clps711x
parent304b2c684e42af5b72d643322f783d88538dc817 (diff)
ARM: clps711x: Combine header files into one for clps711x-targets
Current ARM7 Cirrus Logic product line contains only 3 cpu. EP7312 - Fully functional. EP7309 - Missing SDRAM interface. EP7311 - Missing DAI. It makes no sense to separate the header files to identify these differences, it is only necessary to keep in mind the presence or lack of any features of a specific CPU when writing code. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-clps711x')
-rw-r--r--arch/arm/mach-clps711x/Kconfig21
-rw-r--r--arch/arm/mach-clps711x/include/mach/hardware.h23
2 files changed, 4 insertions, 40 deletions
diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
index eb34bd1251d..ea036d62158 100644
--- a/arch/arm/mach-clps711x/Kconfig
+++ b/arch/arm/mach-clps711x/Kconfig
@@ -1,6 +1,6 @@
if ARCH_CLPS711X
-menu "CLPS711X/EP721X Implementations"
+menu "CLPS711X/EP721X/EP731X Implementations"
config ARCH_AUTCPU12
bool "AUTCPU12"
@@ -45,26 +45,13 @@ config ARCH_P720T
config ARCH_FORTUNET
bool "FORTUNET"
-# XXX Maybe these should indicate register compatibility
-# instead of being mutually exclusive.
-config ARCH_EP7211
- bool
- depends on ARCH_EDB7211
- default y
-
-config ARCH_EP7212
- bool
- depends on ARCH_P720T || ARCH_CEIVA
- default y
-
config EP72XX_ROM_BOOT
- bool "EP72xx ROM boot"
- depends on ARCH_EP7211 || ARCH_EP7212
- ---help---
+ bool "EP721x/EP731x ROM boot"
+ help
If you say Y here, your CLPS711x-based kernel will use the bootstrap
mode memory map instead of the normal memory map.
- Processors derived from the Cirrus CLPS-711X core support two boot
+ Processors derived from the Cirrus CLPS711X core support two boot
modes. Normal mode boots from the external memory device at CS0.
Bootstrap mode rearranges parts of the memory map, placing an
internal 128 byte bootstrap ROM at CS0. This option performs the
diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h
index 1026ac96870..d31fc791f51 100644
--- a/arch/arm/mach-clps711x/include/mach/hardware.h
+++ b/arch/arm/mach-clps711x/include/mach/hardware.h
@@ -61,32 +61,11 @@
#define CS7_PHYS_BASE (0x00000000)
#endif
-#if defined (CONFIG_ARCH_EP7211)
-
-#include <asm/hardware/ep7211.h>
-
-#elif defined (CONFIG_ARCH_EP7212)
-
-#include <asm/hardware/ep7212.h>
-
-#endif
-
#define SYSPLD_VIRT_BASE 0xfe000000
#define SYSPLD_BASE SYSPLD_VIRT_BASE
-#if defined (CONFIG_ARCH_AUTCPU12)
-
-#include <asm/hardware/ep7212.h>
-#include <asm/hardware/cs89712.h>
-
-#endif
-
-
#if defined (CONFIG_ARCH_CDB89712)
-#include <asm/hardware/ep7212.h>
-#include <asm/hardware/cs89712.h>
-
#define ETHER_START 0x20000000
#define ETHER_SIZE 0x1000
#define ETHER_BASE 0xfe000000
@@ -149,8 +128,6 @@
#if defined (CONFIG_ARCH_CEIVA)
-#include <asm/hardware/ep7212.h>
-
/*
* The two flash banks are wired to chip selects 0 and 1. This is the mapping
* for them.