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authorPritesh Raithatha <praithatha@nvidia.com>2012-10-30 15:37:09 +0530
committerStephen Warren <swarren@nvidia.com>2012-10-30 14:37:06 -0600
commit322337b8fbd8c392246529d5db924820fc0c7381 (patch)
tree2df45f2bb857eb1d816a0af1c8e8880d06ad11d2 /arch/arm/boot/dts/tegra30.dtsi
parent8f0d8163b50e01f398b14bcd4dc039ac5ab18d64 (diff)
ARM: dt: tegra: fix length of pad control and mux registers
The reg property contains <base length> not <base last_offset>. Fix the length values to be length not last_offset. Cc: stable@vger.kernel.org Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra30.dtsi')
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index b1497c7d7d6..df7f2270fc9 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -73,8 +73,8 @@
pinmux: pinmux {
compatible = "nvidia,tegra30-pinmux";
- reg = <0x70000868 0xd0 /* Pad control registers */
- 0x70003000 0x3e0>; /* Mux registers */
+ reg = <0x70000868 0xd4 /* Pad control registers */
+ 0x70003000 0x3e4>; /* Mux registers */
};
serial@70006000 {