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authorLinus Torvalds <torvalds@linux-foundation.org>2012-12-19 13:05:22 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2012-12-19 13:05:22 -0800
commit2f0bf92513be58d2d65c0a4cc05c5779a7cd81e1 (patch)
tree969737816b237a6b920253e92cdac5dec99f04b5 /Documentation
parent1bd12c91de35756129b8ffe28a4fe45177b86381 (diff)
parent055d4db1e1ef6f983c3565110fbe6737087e9103 (diff)
Merge tag 'xtensa-20121218' of git://github.com/czankel/xtensa-linux
Pull Xtensa patchset from Chris Zankel: "This contains support of device trees, many fixes, and code clean-ups" * tag 'xtensa-20121218' of git://github.com/czankel/xtensa-linux: (33 commits) xtensa: don't try to build DTB when OF is disabled xtensa: set the correct ethernet address for xtfpga xtensa: clean up files to make them code-style compliant xtensa: provide endianness macro for sparse xtensa: fix RASID SR initialization xtensa: initialize CPENABLE SR when core has one xtensa: reset all timers on initialization Use for_each_compatible_node() macro. xtensa: add XTFPGA DTS xtensa: add support for the XTFPGA boards xtensa: add device trees support xtensa: add IRQ domains support xtensa: add U-Boot image support (uImage). xtensa: clean up boot make rules xtensa: fix mb and wmb definitions xtensa: add s32c1i-based spinlock implementations xtensa: add s32c1i-based bitops implementations xtensa: add s32c1i-based atomic ops implementations xtensa: add s32c1i sanity check xtensa: add trap_set_handler function ...
Diffstat (limited to 'Documentation')
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+We Have Atomic Operation Control (ATOMCTL) Register.
+This register determines the effect of using a S32C1I instruction
+with various combinations of:
+
+ 1. With and without an Coherent Cache Controller which
+ can do Atomic Transactions to the memory internally.
+
+ 2. With and without An Intelligent Memory Controller which
+ can do Atomic Transactions itself.
+
+The Core comes up with a default value of for the three types of cache ops:
+
+ 0x28: (WB: Internal, WT: Internal, BY:Exception)
+
+On the FPGA Cards we typically simulate an Intelligent Memory controller
+which can implement RCW transactions. For FPGA cards with an External
+Memory controller we let it to the atomic operations internally while
+doing a Cached (WB) transaction and use the Memory RCW for un-cached
+operations.
+
+For systems without an coherent cache controller, non-MX, we always
+use the memory controllers RCW, thought non-MX controlers likely
+support the Internal Operation.
+
+CUSTOMER-WARNING:
+ Virtually all customers buy their memory controllers from vendors that
+ don't support atomic RCW memory transactions and will likely want to
+ configure this register to not use RCW.
+
+Developers might find using RCW in Bypass mode convenient when testing
+with the cache being bypassed; for example studying cache alias problems.
+
+See Section 4.3.12.4 of ISA; Bits:
+
+ WB WT BY
+ 5 4 | 3 2 | 1 0
+ 2 Bit
+ Field
+ Values WB - Write Back WT - Write Thru BY - Bypass
+--------- --------------- ----------------- ----------------
+ 0 Exception Exception Exception
+ 1 RCW Transaction RCW Transaction RCW Transaction
+ 2 Internal Operation Exception Reserved
+ 3 Reserved Reserved Reserved