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authorSascha Hauer <s.hauer@pengutronix.de>2012-11-21 14:42:31 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2012-11-22 15:32:33 +0100
commit7a04092c733fd72ded1294719046cfdb31feced3 (patch)
tree2505ec2958480a8a06b5d11c07eb191bbf6ed8e0 /Documentation/devicetree/bindings/clock/imx6q-clock.txt
parent13861701a83765cc442ffe9bac0126ec75a3342e (diff)
ARM i.MX6: Fix ethernet PLL clocks
In current code the ethernet PLL is not handled correctly. The PLL runs at 500MHz and has different outputs. Only the enet reference clock is implemented. This patch changes the PLL so that it outputs 500MHz and adds the additional outputs as dividers. This now matches the datasheet which says: > This PLL synthesizes a low jitter clock from 24 MHz reference clock. > The PLL outputs a 500 MHz clock. The reference clocks generated by this PLL are: > • Ref_PCIe = 125 MHz > • Ref_SATA = 100 MHz > • Ref_ethernet, which is configurable based on the PLL_ENET[1:0] register field. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/clock/imx6q-clock.txt')
-rw-r--r--Documentation/devicetree/bindings/clock/imx6q-clock.txt5
1 files changed, 5 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
index bb71d4f8004..d77b4e68dc4 100644
--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -198,6 +198,11 @@ clocks and IDs.
usbphy2 183
ldb_di0_div_3_5 184
ldb_di1_div_3_5 185
+ sata_ref 186
+ sata_ref_100m 187
+ pcie_ref 188
+ pcie_ref_125m 189
+ enet_ref 190
Examples: