arm64: Kernel booting and initialisation
The patch adds the kernel booting and the initial setup code. Documentation/arm64/booting.txt describes the booting protocol on the AArch64 Linux kernel. This is subject to change following the work on boot standardisation, ACPI. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
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Catalin Marinas
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Booting AArch64 Linux
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=====================
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Author: Will Deacon <will.deacon@arm.com>
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Date : 07 September 2012
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This document is based on the ARM booting document by Russell King and
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is relevant to all public releases of the AArch64 Linux kernel.
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The AArch64 exception model is made up of a number of exception levels
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(EL0 - EL3), with EL0 and EL1 having a secure and a non-secure
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counterpart. EL2 is the hypervisor level and exists only in non-secure
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mode. EL3 is the highest priority level and exists only in secure mode.
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For the purposes of this document, we will use the term `boot loader'
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simply to define all software that executes on the CPU(s) before control
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is passed to the Linux kernel. This may include secure monitor and
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hypervisor code, or it may just be a handful of instructions for
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preparing a minimal boot environment.
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Essentially, the boot loader should provide (as a minimum) the
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following:
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1. Setup and initialise the RAM
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2. Setup the device tree
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3. Decompress the kernel image
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4. Call the kernel image
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1. Setup and initialise RAM
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---------------------------
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Requirement: MANDATORY
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The boot loader is expected to find and initialise all RAM that the
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kernel will use for volatile data storage in the system. It performs
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this in a machine dependent manner. (It may use internal algorithms
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to automatically locate and size all RAM, or it may use knowledge of
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the RAM in the machine, or any other method the boot loader designer
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sees fit.)
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2. Setup the device tree
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-------------------------
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Requirement: MANDATORY
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The device tree blob (dtb) must be no bigger than 2 megabytes in size
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and placed at a 2-megabyte boundary within the first 512 megabytes from
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the start of the kernel image. This is to allow the kernel to map the
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blob using a single section mapping in the initial page tables.
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3. Decompress the kernel image
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------------------------------
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Requirement: OPTIONAL
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The AArch64 kernel does not currently provide a decompressor and
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therefore requires decompression (gzip etc.) to be performed by the boot
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loader if a compressed Image target (e.g. Image.gz) is used. For
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bootloaders that do not implement this requirement, the uncompressed
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Image target is available instead.
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4. Call the kernel image
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------------------------
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Requirement: MANDATORY
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The decompressed kernel image contains a 32-byte header as follows:
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u32 magic = 0x14000008; /* branch to stext, little-endian */
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u32 res0 = 0; /* reserved */
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u64 text_offset; /* Image load offset */
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u64 res1 = 0; /* reserved */
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u64 res2 = 0; /* reserved */
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The image must be placed at the specified offset (currently 0x80000)
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from the start of the system RAM and called there. The start of the
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system RAM must be aligned to 2MB.
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Before jumping into the kernel, the following conditions must be met:
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- Quiesce all DMA capable devices so that memory does not get
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corrupted by bogus network packets or disk data. This will save
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you many hours of debug.
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- Primary CPU general-purpose register settings
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x0 = physical address of device tree blob (dtb) in system RAM.
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x1 = 0 (reserved for future use)
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x2 = 0 (reserved for future use)
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x3 = 0 (reserved for future use)
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- CPU mode
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All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
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IRQ and FIQ).
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The CPU must be in either EL2 (RECOMMENDED in order to have access to
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the virtualisation extensions) or non-secure EL1.
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- Caches, MMUs
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The MMU must be off.
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Instruction cache may be on or off.
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Data cache must be off and invalidated.
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External caches (if present) must be configured and disabled.
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- Architected timers
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CNTFRQ must be programmed with the timer frequency.
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If entering the kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0)
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set where available.
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- Coherency
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All CPUs to be booted by the kernel must be part of the same coherency
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domain on entry to the kernel. This may require IMPLEMENTATION DEFINED
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initialisation to enable the receiving of maintenance operations on
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each CPU.
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- System registers
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All writable architected system registers at the exception level where
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the kernel image will be entered must be initialised by software at a
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higher exception level to prevent execution in an UNKNOWN state.
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The boot loader is expected to enter the kernel on each CPU in the
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following manner:
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- The primary CPU must jump directly to the first instruction of the
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kernel image. The device tree blob passed by this CPU must contain
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for each CPU node:
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1. An 'enable-method' property. Currently, the only supported value
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for this field is the string "spin-table".
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2. A 'cpu-release-addr' property identifying a 64-bit,
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zero-initialised memory location.
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It is expected that the bootloader will generate these device tree
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properties and insert them into the blob prior to kernel entry.
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- Any secondary CPUs must spin outside of the kernel in a reserved area
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of memory (communicated to the kernel by a /memreserve/ region in the
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device tree) polling their cpu-release-addr location, which must be
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contained in the reserved region. A wfe instruction may be inserted
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to reduce the overhead of the busy-loop and a sev will be issued by
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the primary CPU. When a read of the location pointed to by the
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cpu-release-addr returns a non-zero value, the CPU must jump directly
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to this value.
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- Secondary CPU general-purpose register settings
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x0 = 0 (reserved for future use)
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x1 = 0 (reserved for future use)
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x2 = 0 (reserved for future use)
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x3 = 0 (reserved for future use)
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@ -0,0 +1,26 @@
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/*
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* Based on arch/arm/include/asm/setup.h
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*
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* Copyright (C) 1997-1999 Russell King
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_SETUP_H
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#define __ASM_SETUP_H
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#include <linux/types.h>
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#define COMMAND_LINE_SIZE 2048
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#endif
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@ -0,0 +1,510 @@
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/*
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* Low-level CPU initialisation
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* Based on arch/arm/kernel/head.S
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*
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* Copyright (C) 1994-2002 Russell King
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* Copyright (C) 2003-2012 ARM Ltd.
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* Authors: Catalin Marinas <catalin.marinas@arm.com>
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* Will Deacon <will.deacon@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/ptrace.h>
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#include <asm/asm-offsets.h>
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#include <asm/memory.h>
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#include <asm/thread_info.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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/*
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* swapper_pg_dir is the virtual address of the initial page table. We place
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* the page tables 3 * PAGE_SIZE below KERNEL_RAM_VADDR. The idmap_pg_dir has
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* 2 pages and is placed below swapper_pg_dir.
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*/
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#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
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#if (KERNEL_RAM_VADDR & 0xfffff) != 0x80000
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#error KERNEL_RAM_VADDR must start at 0xXXX80000
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#endif
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#define SWAPPER_DIR_SIZE (3 * PAGE_SIZE)
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#define IDMAP_DIR_SIZE (2 * PAGE_SIZE)
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.globl swapper_pg_dir
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.equ swapper_pg_dir, KERNEL_RAM_VADDR - SWAPPER_DIR_SIZE
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.globl idmap_pg_dir
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.equ idmap_pg_dir, swapper_pg_dir - IDMAP_DIR_SIZE
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.macro pgtbl, ttb0, ttb1, phys
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add \ttb1, \phys, #TEXT_OFFSET - SWAPPER_DIR_SIZE
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sub \ttb0, \ttb1, #IDMAP_DIR_SIZE
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.endm
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#ifdef CONFIG_ARM64_64K_PAGES
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#define BLOCK_SHIFT PAGE_SHIFT
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#define BLOCK_SIZE PAGE_SIZE
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#else
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#define BLOCK_SHIFT SECTION_SHIFT
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#define BLOCK_SIZE SECTION_SIZE
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#endif
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#define KERNEL_START KERNEL_RAM_VADDR
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#define KERNEL_END _end
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/*
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* Initial memory map attributes.
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*/
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#ifndef CONFIG_SMP
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#define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF
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#define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF
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#else
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#define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF | PTE_SHARED
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#define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S
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#endif
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#ifdef CONFIG_ARM64_64K_PAGES
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#define MM_MMUFLAGS PTE_ATTRINDX(MT_NORMAL) | PTE_FLAGS
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#define IO_MMUFLAGS PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_XN | PTE_FLAGS
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#else
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#define MM_MMUFLAGS PMD_ATTRINDX(MT_NORMAL) | PMD_FLAGS
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#define IO_MMUFLAGS PMD_ATTRINDX(MT_DEVICE_nGnRE) | PMD_SECT_XN | PMD_FLAGS
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#endif
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/*
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* Kernel startup entry point.
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* ---------------------------
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*
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* The requirements are:
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* MMU = off, D-cache = off, I-cache = on or off,
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* x0 = physical address to the FDT blob.
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*
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* This code is mostly position independent so you call this at
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* __pa(PAGE_OFFSET + TEXT_OFFSET).
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*
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* Note that the callee-saved registers are used for storing variables
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* that are useful before the MMU is enabled. The allocations are described
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* in the entry routines.
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*/
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__HEAD
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/*
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* DO NOT MODIFY. Image header expected by Linux boot-loaders.
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*/
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b stext // branch to kernel start, magic
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.long 0 // reserved
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.quad TEXT_OFFSET // Image load offset from start of RAM
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.quad 0 // reserved
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.quad 0 // reserved
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ENTRY(stext)
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mov x21, x0 // x21=FDT
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bl el2_setup // Drop to EL1
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mrs x22, midr_el1 // x22=cpuid
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mov x0, x22
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bl lookup_processor_type
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mov x23, x0 // x23=current cpu_table
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cbz x23, __error_p // invalid processor (x23=0)?
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bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
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bl __vet_fdt
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bl __create_page_tables // x25=TTBR0, x26=TTBR1
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/*
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* The following calls CPU specific code in a position independent
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* manner. See arch/arm64/mm/proc.S for details. x23 = base of
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* cpu_info structure selected by lookup_processor_type above.
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* On return, the CPU will be ready for the MMU to be turned on and
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* the TCR will have been set.
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*/
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ldr x27, __switch_data // address to jump to after
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// MMU has been enabled
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adr lr, __enable_mmu // return (PIC) address
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ldr x12, [x23, #CPU_INFO_SETUP]
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add x12, x12, x28 // __virt_to_phys
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br x12 // initialise processor
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ENDPROC(stext)
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/*
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* If we're fortunate enough to boot at EL2, ensure that the world is
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* sane before dropping to EL1.
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*/
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ENTRY(el2_setup)
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mrs x0, CurrentEL
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cmp x0, #PSR_MODE_EL2t
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ccmp x0, #PSR_MODE_EL2h, #0x4, ne
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b.eq 1f
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ret
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/* Hyp configuration. */
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1: mov x0, #(1 << 31) // 64-bit EL1
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msr hcr_el2, x0
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/* Generic timers. */
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mrs x0, cnthctl_el2
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orr x0, x0, #3 // Enable EL1 physical timers
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msr cnthctl_el2, x0
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/* Populate ID registers. */
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mrs x0, midr_el1
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mrs x1, mpidr_el1
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msr vpidr_el2, x0
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msr vmpidr_el2, x1
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/* sctlr_el1 */
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mov x0, #0x0800 // Set/clear RES{1,0} bits
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movk x0, #0x30d0, lsl #16
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msr sctlr_el1, x0
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/* Coprocessor traps. */
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mov x0, #0x33ff
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msr cptr_el2, x0 // Disable copro. traps to EL2
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#ifdef CONFIG_COMPAT
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msr hstr_el2, xzr // Disable CP15 traps to EL2
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#endif
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/* spsr */
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mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
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PSR_MODE_EL1h)
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msr spsr_el2, x0
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msr elr_el2, lr
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eret
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ENDPROC(el2_setup)
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.align 3
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2: .quad .
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.quad PAGE_OFFSET
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#ifdef CONFIG_SMP
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.pushsection .smp.pen.text, "ax"
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.align 3
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1: .quad .
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.quad secondary_holding_pen_release
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/*
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* This provides a "holding pen" for platforms to hold all secondary
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* cores are held until we're ready for them to initialise.
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*/
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ENTRY(secondary_holding_pen)
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bl el2_setup // Drop to EL1
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mrs x0, mpidr_el1
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and x0, x0, #15 // CPU number
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adr x1, 1b
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ldp x2, x3, [x1]
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sub x1, x1, x2
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add x3, x3, x1
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pen: ldr x4, [x3]
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cmp x4, x0
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b.eq secondary_startup
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wfe
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b pen
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ENDPROC(secondary_holding_pen)
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.popsection
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ENTRY(secondary_startup)
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/*
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* Common entry point for secondary CPUs.
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*/
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mrs x22, midr_el1 // x22=cpuid
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mov x0, x22
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bl lookup_processor_type
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mov x23, x0 // x23=current cpu_table
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cbz x23, __error_p // invalid processor (x23=0)?
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bl __calc_phys_offset // x24=phys offset
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pgtbl x25, x26, x24 // x25=TTBR0, x26=TTBR1
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ldr x12, [x23, #CPU_INFO_SETUP]
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add x12, x12, x28 // __virt_to_phys
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blr x12 // initialise processor
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ldr x21, =secondary_data
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ldr x27, =__secondary_switched // address to jump to after enabling the MMU
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b __enable_mmu
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ENDPROC(secondary_startup)
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ENTRY(__secondary_switched)
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ldr x0, [x21] // get secondary_data.stack
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mov sp, x0
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mov x29, #0
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b secondary_start_kernel
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ENDPROC(__secondary_switched)
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#endif /* CONFIG_SMP */
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/*
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* Setup common bits before finally enabling the MMU. Essentially this is just
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* loading the page table pointer and vector base registers.
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*
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* On entry to this code, x0 must contain the SCTLR_EL1 value for turning on
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* the MMU.
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*/
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__enable_mmu:
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ldr x5, =vectors
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msr vbar_el1, x5
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msr ttbr0_el1, x25 // load TTBR0
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msr ttbr1_el1, x26 // load TTBR1
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isb
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b __turn_mmu_on
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ENDPROC(__enable_mmu)
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/*
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* Enable the MMU. This completely changes the structure of the visible memory
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* space. You will not be able to trace execution through this.
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*
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* x0 = system control register
|
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* x27 = *virtual* address to jump to upon completion
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*
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* other registers depend on the function called upon completion
|
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*/
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.align 6
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__turn_mmu_on:
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msr sctlr_el1, x0
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isb
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br x27
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ENDPROC(__turn_mmu_on)
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/*
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* Calculate the start of physical memory.
|
||||
*/
|
||||
__calc_phys_offset:
|
||||
adr x0, 1f
|
||||
ldp x1, x2, [x0]
|
||||
sub x28, x0, x1 // x28 = PHYS_OFFSET - PAGE_OFFSET
|
||||
add x24, x2, x28 // x24 = PHYS_OFFSET
|
||||
ret
|
||||
ENDPROC(__calc_phys_offset)
|
||||
|
||||
.align 3
|
||||
1: .quad .
|
||||
.quad PAGE_OFFSET
|
||||
|
||||
/*
|
||||
* Macro to populate the PGD for the corresponding block entry in the next
|
||||
* level (tbl) for the given virtual address.
|
||||
*
|
||||
* Preserves: pgd, tbl, virt
|
||||
* Corrupts: tmp1, tmp2
|
||||
*/
|
||||
.macro create_pgd_entry, pgd, tbl, virt, tmp1, tmp2
|
||||
lsr \tmp1, \virt, #PGDIR_SHIFT
|
||||
and \tmp1, \tmp1, #PTRS_PER_PGD - 1 // PGD index
|
||||
orr \tmp2, \tbl, #3 // PGD entry table type
|
||||
str \tmp2, [\pgd, \tmp1, lsl #3]
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Macro to populate block entries in the page table for the start..end
|
||||
* virtual range (inclusive).
|
||||
*
|
||||
* Preserves: tbl, flags
|
||||
* Corrupts: phys, start, end, pstate
|
||||
*/
|
||||
.macro create_block_map, tbl, flags, phys, start, end, idmap=0
|
||||
lsr \phys, \phys, #BLOCK_SHIFT
|
||||
.if \idmap
|
||||
and \start, \phys, #PTRS_PER_PTE - 1 // table index
|
||||
.else
|
||||
lsr \start, \start, #BLOCK_SHIFT
|
||||
and \start, \start, #PTRS_PER_PTE - 1 // table index
|
||||
.endif
|
||||
orr \phys, \flags, \phys, lsl #BLOCK_SHIFT // table entry
|
||||
.ifnc \start,\end
|
||||
lsr \end, \end, #BLOCK_SHIFT
|
||||
and \end, \end, #PTRS_PER_PTE - 1 // table end index
|
||||
.endif
|
||||
9999: str \phys, [\tbl, \start, lsl #3] // store the entry
|
||||
.ifnc \start,\end
|
||||
add \start, \start, #1 // next entry
|
||||
add \phys, \phys, #BLOCK_SIZE // next block
|
||||
cmp \start, \end
|
||||
b.ls 9999b
|
||||
.endif
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Setup the initial page tables. We only setup the barest amount which is
|
||||
* required to get the kernel running. The following sections are required:
|
||||
* - identity mapping to enable the MMU (low address, TTBR0)
|
||||
* - first few MB of the kernel linear mapping to jump to once the MMU has
|
||||
* been enabled, including the FDT blob (TTBR1)
|
||||
*/
|
||||
__create_page_tables:
|
||||
pgtbl x25, x26, x24 // idmap_pg_dir and swapper_pg_dir addresses
|
||||
|
||||
/*
|
||||
* Clear the idmap and swapper page tables.
|
||||
*/
|
||||
mov x0, x25
|
||||
add x6, x26, #SWAPPER_DIR_SIZE
|
||||
1: stp xzr, xzr, [x0], #16
|
||||
stp xzr, xzr, [x0], #16
|
||||
stp xzr, xzr, [x0], #16
|
||||
stp xzr, xzr, [x0], #16
|
||||
cmp x0, x6
|
||||
b.lo 1b
|
||||
|
||||
ldr x7, =MM_MMUFLAGS
|
||||
|
||||
/*
|
||||
* Create the identity mapping.
|
||||
*/
|
||||
add x0, x25, #PAGE_SIZE // section table address
|
||||
adr x3, __turn_mmu_on // virtual/physical address
|
||||
create_pgd_entry x25, x0, x3, x5, x6
|
||||
create_block_map x0, x7, x3, x5, x5, idmap=1
|
||||
|
||||
/*
|
||||
* Map the kernel image (starting with PHYS_OFFSET).
|
||||
*/
|
||||
add x0, x26, #PAGE_SIZE // section table address
|
||||
mov x5, #PAGE_OFFSET
|
||||
create_pgd_entry x26, x0, x5, x3, x6
|
||||
ldr x6, =KERNEL_END - 1
|
||||
mov x3, x24 // phys offset
|
||||
create_block_map x0, x7, x3, x5, x6
|
||||
|
||||
/*
|
||||
* Map the FDT blob (maximum 2MB; must be within 512MB of
|
||||
* PHYS_OFFSET).
|
||||
*/
|
||||
mov x3, x21 // FDT phys address
|
||||
and x3, x3, #~((1 << 21) - 1) // 2MB aligned
|
||||
mov x6, #PAGE_OFFSET
|
||||
sub x5, x3, x24 // subtract PHYS_OFFSET
|
||||
tst x5, #~((1 << 29) - 1) // within 512MB?
|
||||
csel x21, xzr, x21, ne // zero the FDT pointer
|
||||
b.ne 1f
|
||||
add x5, x5, x6 // __va(FDT blob)
|
||||
add x6, x5, #1 << 21 // 2MB for the FDT blob
|
||||
sub x6, x6, #1 // inclusive range
|
||||
create_block_map x0, x7, x3, x5, x6
|
||||
1:
|
||||
ret
|
||||
ENDPROC(__create_page_tables)
|
||||
.ltorg
|
||||
|
||||
.align 3
|
||||
.type __switch_data, %object
|
||||
__switch_data:
|
||||
.quad __mmap_switched
|
||||
.quad __data_loc // x4
|
||||
.quad _data // x5
|
||||
.quad __bss_start // x6
|
||||
.quad _end // x7
|
||||
.quad processor_id // x4
|
||||
.quad __fdt_pointer // x5
|
||||
.quad memstart_addr // x6
|
||||
.quad init_thread_union + THREAD_START_SP // sp
|
||||
|
||||
/*
|
||||
* The following fragment of code is executed with the MMU on in MMU mode, and
|
||||
* uses absolute addresses; this is not position independent.
|
||||
*/
|
||||
__mmap_switched:
|
||||
adr x3, __switch_data + 8
|
||||
|
||||
ldp x4, x5, [x3], #16
|
||||
ldp x6, x7, [x3], #16
|
||||
cmp x4, x5 // Copy data segment if needed
|
||||
1: ccmp x5, x6, #4, ne
|
||||
b.eq 2f
|
||||
ldr x16, [x4], #8
|
||||
str x16, [x5], #8
|
||||
b 1b
|
||||
2:
|
||||
1: cmp x6, x7
|
||||
b.hs 2f
|
||||
str xzr, [x6], #8 // Clear BSS
|
||||
b 1b
|
||||
2:
|
||||
ldp x4, x5, [x3], #16
|
||||
ldr x6, [x3], #8
|
||||
ldr x16, [x3]
|
||||
mov sp, x16
|
||||
str x22, [x4] // Save processor ID
|
||||
str x21, [x5] // Save FDT pointer
|
||||
str x24, [x6] // Save PHYS_OFFSET
|
||||
mov x29, #0
|
||||
b start_kernel
|
||||
ENDPROC(__mmap_switched)
|
||||
|
||||
/*
|
||||
* Exception handling. Something went wrong and we can't proceed. We ought to
|
||||
* tell the user, but since we don't have any guarantee that we're even
|
||||
* running on the right architecture, we do virtually nothing.
|
||||
*/
|
||||
__error_p:
|
||||
ENDPROC(__error_p)
|
||||
|
||||
__error:
|
||||
1: nop
|
||||
b 1b
|
||||
ENDPROC(__error)
|
||||
|
||||
/*
|
||||
* This function gets the processor ID in w0 and searches the cpu_table[] for
|
||||
* a match. It returns a pointer to the struct cpu_info it found. The
|
||||
* cpu_table[] must end with an empty (all zeros) structure.
|
||||
*
|
||||
* This routine can be called via C code and it needs to work with the MMU
|
||||
* both disabled and enabled (the offset is calculated automatically).
|
||||
*/
|
||||
ENTRY(lookup_processor_type)
|
||||
adr x1, __lookup_processor_type_data
|
||||
ldp x2, x3, [x1]
|
||||
sub x1, x1, x2 // get offset between VA and PA
|
||||
add x3, x3, x1 // convert VA to PA
|
||||
1:
|
||||
ldp w5, w6, [x3] // load cpu_id_val and cpu_id_mask
|
||||
cbz w5, 2f // end of list?
|
||||
and w6, w6, w0
|
||||
cmp w5, w6
|
||||
b.eq 3f
|
||||
add x3, x3, #CPU_INFO_SZ
|
||||
b 1b
|
||||
2:
|
||||
mov x3, #0 // unknown processor
|
||||
3:
|
||||
mov x0, x3
|
||||
ret
|
||||
ENDPROC(lookup_processor_type)
|
||||
|
||||
.align 3
|
||||
.type __lookup_processor_type_data, %object
|
||||
__lookup_processor_type_data:
|
||||
.quad .
|
||||
.quad cpu_table
|
||||
.size __lookup_processor_type_data, . - __lookup_processor_type_data
|
||||
|
||||
/*
|
||||
* Determine validity of the x21 FDT pointer.
|
||||
* The dtb must be 8-byte aligned and live in the first 512M of memory.
|
||||
*/
|
||||
__vet_fdt:
|
||||
tst x21, #0x7
|
||||
b.ne 1f
|
||||
cmp x21, x24
|
||||
b.lt 1f
|
||||
mov x0, #(1 << 29)
|
||||
add x0, x0, x24
|
||||
cmp x21, x0
|
||||
b.ge 1f
|
||||
ret
|
||||
1:
|
||||
mov x21, #0
|
||||
ret
|
||||
ENDPROC(__vet_fdt)
|
||||
|
|
@ -0,0 +1,347 @@
|
|||
/*
|
||||
* Based on arch/arm/kernel/setup.c
|
||||
*
|
||||
* Copyright (C) 1995-2001 Russell King
|
||||
* Copyright (C) 2012 ARM Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <linux/export.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/stddef.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/utsname.h>
|
||||
#include <linux/initrd.h>
|
||||
#include <linux/console.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/screen_info.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kexec.h>
|
||||
#include <linux/crash_dump.h>
|
||||
#include <linux/root_dev.h>
|
||||
#include <linux/cpu.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/proc_fs.h>
|
||||
#include <linux/memblock.h>
|
||||
#include <linux/of_fdt.h>
|
||||
|
||||
#include <asm/cputype.h>
|
||||
#include <asm/elf.h>
|
||||
#include <asm/cputable.h>
|
||||
#include <asm/sections.h>
|
||||
#include <asm/setup.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/tlbflush.h>
|
||||
#include <asm/traps.h>
|
||||
#include <asm/memblock.h>
|
||||
|
||||
unsigned int processor_id;
|
||||
EXPORT_SYMBOL(processor_id);
|
||||
|
||||
unsigned int elf_hwcap __read_mostly;
|
||||
EXPORT_SYMBOL_GPL(elf_hwcap);
|
||||
|
||||
static const char *cpu_name;
|
||||
static const char *machine_name;
|
||||
phys_addr_t __fdt_pointer __initdata;
|
||||
|
||||
/*
|
||||
* Standard memory resources
|
||||
*/
|
||||
static struct resource mem_res[] = {
|
||||
{
|
||||
.name = "Kernel code",
|
||||
.start = 0,
|
||||
.end = 0,
|
||||
.flags = IORESOURCE_MEM
|
||||
},
|
||||
{
|
||||
.name = "Kernel data",
|
||||
.start = 0,
|
||||
.end = 0,
|
||||
.flags = IORESOURCE_MEM
|
||||
}
|
||||
};
|
||||
|
||||
#define kernel_code mem_res[0]
|
||||
#define kernel_data mem_res[1]
|
||||
|
||||
void __init early_print(const char *str, ...)
|
||||
{
|
||||
char buf[256];
|
||||
va_list ap;
|
||||
|
||||
va_start(ap, str);
|
||||
vsnprintf(buf, sizeof(buf), str, ap);
|
||||
va_end(ap);
|
||||
|
||||
printk("%s", buf);
|
||||
}
|
||||
|
||||
static void __init setup_processor(void)
|
||||
{
|
||||
struct cpu_info *cpu_info;
|
||||
|
||||
/*
|
||||
* locate processor in the list of supported processor
|
||||
* types. The linker builds this table for us from the
|
||||
* entries in arch/arm/mm/proc.S
|
||||
*/
|
||||
cpu_info = lookup_processor_type(read_cpuid_id());
|
||||
if (!cpu_info) {
|
||||
printk("CPU configuration botched (ID %08x), unable to continue.\n",
|
||||
read_cpuid_id());
|
||||
while (1);
|
||||
}
|
||||
|
||||
cpu_name = cpu_info->cpu_name;
|
||||
|
||||
printk("CPU: %s [%08x] revision %d\n",
|
||||
cpu_name, read_cpuid_id(), read_cpuid_id() & 15);
|
||||
|
||||
sprintf(init_utsname()->machine, "aarch64");
|
||||
elf_hwcap = 0;
|
||||
}
|
||||
|
||||
static void __init setup_machine_fdt(phys_addr_t dt_phys)
|
||||
{
|
||||
struct boot_param_header *devtree;
|
||||
unsigned long dt_root;
|
||||
|
||||
/* Check we have a non-NULL DT pointer */
|
||||
if (!dt_phys) {
|
||||
early_print("\n"
|
||||
"Error: NULL or invalid device tree blob\n"
|
||||
"The dtb must be 8-byte aligned and passed in the first 512MB of memory\n"
|
||||
"\nPlease check your bootloader.\n");
|
||||
|
||||
while (true)
|
||||
cpu_relax();
|
||||
|
||||
}
|
||||
|
||||
devtree = phys_to_virt(dt_phys);
|
||||
|
||||
/* Check device tree validity */
|
||||
if (be32_to_cpu(devtree->magic) != OF_DT_HEADER) {
|
||||
early_print("\n"
|
||||
"Error: invalid device tree blob at physical address 0x%p (virtual address 0x%p)\n"
|
||||
"Expected 0x%x, found 0x%x\n"
|
||||
"\nPlease check your bootloader.\n",
|
||||
dt_phys, devtree, OF_DT_HEADER,
|
||||
be32_to_cpu(devtree->magic));
|
||||
|
||||
while (true)
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
initial_boot_params = devtree;
|
||||
dt_root = of_get_flat_dt_root();
|
||||
|
||||
machine_name = of_get_flat_dt_prop(dt_root, "model", NULL);
|
||||
if (!machine_name)
|
||||
machine_name = of_get_flat_dt_prop(dt_root, "compatible", NULL);
|
||||
if (!machine_name)
|
||||
machine_name = "<unknown>";
|
||||
pr_info("Machine: %s\n", machine_name);
|
||||
|
||||
/* Retrieve various information from the /chosen node */
|
||||
of_scan_flat_dt(early_init_dt_scan_chosen, boot_command_line);
|
||||
/* Initialize {size,address}-cells info */
|
||||
of_scan_flat_dt(early_init_dt_scan_root, NULL);
|
||||
/* Setup memory, calling early_init_dt_add_memory_arch */
|
||||
of_scan_flat_dt(early_init_dt_scan_memory, NULL);
|
||||
}
|
||||
|
||||
void __init early_init_dt_add_memory_arch(u64 base, u64 size)
|
||||
{
|
||||
size &= PAGE_MASK;
|
||||
memblock_add(base, size);
|
||||
}
|
||||
|
||||
void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
|
||||
{
|
||||
return __va(memblock_alloc(size, align));
|
||||
}
|
||||
|
||||
/*
|
||||
* Limit the memory size that was specified via FDT.
|
||||
*/
|
||||
static int __init early_mem(char *p)
|
||||
{
|
||||
phys_addr_t limit;
|
||||
|
||||
if (!p)
|
||||
return 1;
|
||||
|
||||
limit = memparse(p, &p) & PAGE_MASK;
|
||||
pr_notice("Memory limited to %lldMB\n", limit >> 20);
|
||||
|
||||
memblock_enforce_memory_limit(limit);
|
||||
|
||||
return 0;
|
||||
}
|
||||
early_param("mem", early_mem);
|
||||
|
||||
static void __init request_standard_resources(void)
|
||||
{
|
||||
struct memblock_region *region;
|
||||
struct resource *res;
|
||||
|
||||
kernel_code.start = virt_to_phys(_text);
|
||||
kernel_code.end = virt_to_phys(_etext - 1);
|
||||
kernel_data.start = virt_to_phys(_sdata);
|
||||
kernel_data.end = virt_to_phys(_end - 1);
|
||||
|
||||
for_each_memblock(memory, region) {
|
||||
res = alloc_bootmem_low(sizeof(*res));
|
||||
res->name = "System RAM";
|
||||
res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
|
||||
res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
|
||||
res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
|
||||
|
||||
request_resource(&iomem_resource, res);
|
||||
|
||||
if (kernel_code.start >= res->start &&
|
||||
kernel_code.end <= res->end)
|
||||
request_resource(res, &kernel_code);
|
||||
if (kernel_data.start >= res->start &&
|
||||
kernel_data.end <= res->end)
|
||||
request_resource(res, &kernel_data);
|
||||
}
|
||||
}
|
||||
|
||||
void __init setup_arch(char **cmdline_p)
|
||||
{
|
||||
setup_processor();
|
||||
|
||||
setup_machine_fdt(__fdt_pointer);
|
||||
|
||||
init_mm.start_code = (unsigned long) _text;
|
||||
init_mm.end_code = (unsigned long) _etext;
|
||||
init_mm.end_data = (unsigned long) _edata;
|
||||
init_mm.brk = (unsigned long) _end;
|
||||
|
||||
*cmdline_p = boot_command_line;
|
||||
|
||||
parse_early_param();
|
||||
|
||||
arm64_memblock_init();
|
||||
|
||||
paging_init();
|
||||
request_standard_resources();
|
||||
|
||||
unflatten_device_tree();
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
smp_init_cpus();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_VT
|
||||
#if defined(CONFIG_VGA_CONSOLE)
|
||||
conswitchp = &vga_con;
|
||||
#elif defined(CONFIG_DUMMY_CONSOLE)
|
||||
conswitchp = &dummy_con;
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
static DEFINE_PER_CPU(struct cpu, cpu_data);
|
||||
|
||||
static int __init topology_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for_each_possible_cpu(i) {
|
||||
struct cpu *cpu = &per_cpu(cpu_data, i);
|
||||
cpu->hotpluggable = 1;
|
||||
register_cpu(cpu, i);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
subsys_initcall(topology_init);
|
||||
|
||||
static const char *hwcap_str[] = {
|
||||
"fp",
|
||||
"asimd",
|
||||
NULL
|
||||
};
|
||||
|
||||
static int c_show(struct seq_file *m, void *v)
|
||||
{
|
||||
int i;
|
||||
|
||||
seq_printf(m, "Processor\t: %s rev %d (%s)\n",
|
||||
cpu_name, read_cpuid_id() & 15, ELF_PLATFORM);
|
||||
|
||||
for_each_online_cpu(i) {
|
||||
/*
|
||||
* glibc reads /proc/cpuinfo to determine the number of
|
||||
* online processors, looking for lines beginning with
|
||||
* "processor". Give glibc what it expects.
|
||||
*/
|
||||
#ifdef CONFIG_SMP
|
||||
seq_printf(m, "processor\t: %d\n", i);
|
||||
#endif
|
||||
seq_printf(m, "BogoMIPS\t: %lu.%02lu\n\n",
|
||||
loops_per_jiffy / (500000UL/HZ),
|
||||
loops_per_jiffy / (5000UL/HZ) % 100);
|
||||
}
|
||||
|
||||
/* dump out the processor features */
|
||||
seq_puts(m, "Features\t: ");
|
||||
|
||||
for (i = 0; hwcap_str[i]; i++)
|
||||
if (elf_hwcap & (1 << i))
|
||||
seq_printf(m, "%s ", hwcap_str[i]);
|
||||
|
||||
seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24);
|
||||
seq_printf(m, "CPU architecture: AArch64\n");
|
||||
seq_printf(m, "CPU variant\t: 0x%x\n", (read_cpuid_id() >> 20) & 15);
|
||||
seq_printf(m, "CPU part\t: 0x%03x\n", (read_cpuid_id() >> 4) & 0xfff);
|
||||
seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15);
|
||||
|
||||
seq_puts(m, "\n");
|
||||
|
||||
seq_printf(m, "Hardware\t: %s\n", machine_name);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void *c_start(struct seq_file *m, loff_t *pos)
|
||||
{
|
||||
return *pos < 1 ? (void *)1 : NULL;
|
||||
}
|
||||
|
||||
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
|
||||
{
|
||||
++*pos;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void c_stop(struct seq_file *m, void *v)
|
||||
{
|
||||
}
|
||||
|
||||
const struct seq_operations cpuinfo_op = {
|
||||
.start = c_start,
|
||||
.next = c_next,
|
||||
.stop = c_stop,
|
||||
.show = c_show
|
||||
};
|
||||
Reference in New Issue