dect: coa: don't load BMC config twice on TX
Move RX BMC configuration from the radio initialization to the receive functions to avoid double configuration on TX. Signed-off-by: Patrick McHardy <kaber@trash.net>
This commit is contained in:
parent
cbf1cafc33
commit
8e819940f0
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@ -679,7 +679,7 @@ static void sc1442x_tx(const struct dect_transceiver *trx, struct sk_buff *skb)
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sc1442x_to_dmem(dev, off + SD_PREAMBLE_OFF,
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skb_mac_header(skb), skb->mac_len);
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sc1442x_to_dmem(dev, off + SD_DATA_OFF, skb->data, skb->len);
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sc1442x_dwriteb(dev, off + TX_DESC + TRX_DESC_FN, cb->frame);
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sc1442x_dwriteb(dev, off + BMC_TX_CTRL + BMC_CTRL_MFR_OFF, cb->frame);
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/* Init DCS for slots in the first half frame */
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if (ts->flags & DECT_SLOT_CIPHER && slot < DECT_HALF_FRAME_SIZE)
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@ -842,7 +842,7 @@ out:
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dect_transceiver_record_rssi(event, slot, rssi);
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/* Update frame number for next reception */
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sc1442x_dwriteb(dev, off + RX_DESC + TRX_DESC_FN, framenum + 1);
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sc1442x_dwriteb(dev, off + BMC_RX_CTRL + BMC_CTRL_MFR_OFF, framenum + 1);
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/* Init DCS for slots in the first half frame */
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if (ts->flags & DECT_SLOT_CIPHER && slot < DECT_HALF_FRAME_SIZE)
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@ -925,8 +925,8 @@ static void sc1442x_init_slot(const struct coa_device *dev, u8 slot)
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sc1442x_switch_to_bank(dev, banktable[slot]);
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off = sc1442x_slot_offset(slot);
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sc1442x_write_bmc_config(dev, off + TX_DESC, slot < 12, true);
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sc1442x_write_bmc_config(dev, off + RX_DESC, slot < 12, false);
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sc1442x_write_bmc_config(dev, off + BMC_TX_CTRL, slot < 12, true);
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sc1442x_write_bmc_config(dev, off + BMC_RX_CTRL, slot < 12, false);
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dev->radio_ops->rx_init(dev, off);
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dev->radio_ops->tx_init(dev, off);
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}
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@ -994,7 +994,7 @@ int sc1442x_init_device(struct coa_device *dev)
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for (i = 1; i < SC1442X_CC_SIZE; i++)
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sc1442x_dwriteb(dev, DIP_CC_INIT + i, 0);
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sc1442x_write_bmc_config(dev, DIP_RF_INIT, false, false);
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sc1442x_write_bmc_config(dev, BMC_CTRL_INIT, false, false);
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for (slot = 0; slot < DECT_FRAME_SIZE; slot += 2)
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sc1442x_init_slot(dev, slot);
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@ -34,14 +34,21 @@ BANK6_HIGH EQU 0xd0
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BANK7_LOW EQU 0xe0
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BANK7_HIGH EQU 0xf0
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DIP_RF_INIT EQU 0x00
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BMC_CTRL_INIT EQU 0x00
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; Codec Control
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DIP_CC_INIT EQU 0x10
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; Radio configuration word
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RF_DESC EQU 0x3a
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TX_DESC EQU 0x40
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RX_DESC EQU 0x48
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; BMC control information
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BMC_CTRL_SIZE EQU 7
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BMC_TX_CTRL EQU 0x40
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BMC_RX_CTRL EQU 0x48
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; (multi) frame number for scambler and DCS
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BMC_CTRL_MFR_OFF EQU 6
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; Cipher IV/Key
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DCS_DESC EQU 0x50
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@ -52,9 +59,6 @@ DCS_CK EQU DCS_DESC + 0x8
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DCS_STATE EQU 0x70
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DCS_STATE_SIZE EQU 11
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; scrambler frame number offset to {RX,TX}_DESC
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TRX_DESC_FN EQU 0x06
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SD_PREAMBLE_OFF EQU 0x01
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SD_A_FIELD_OFF EQU 0x06
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SD_B_FIELD_OFF EQU 0x0E
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@ -205,7 +209,10 @@ label_58: B_RST
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; Enable the receiver, receive the S-field and the first 61 bits of the D-field
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; (93 bits total)
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;
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Receive: P_LDH PB_RX_ON
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Receive: B_RST
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B_RC BMC_RX_CTRL
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WT BMC_CTRL_SIZE + 1
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P_LDH PB_RX_ON
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P_LDL PB_RSSI ; enable RSSI measurement
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WT 25
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WNT 1 ; Wait until beginning of slot |
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@ -224,7 +231,10 @@ ClockSyncOff: P_SC 0x00 ; | p: 30 S: 46
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WT 62 ; Receive first 61 bits of A-field | p: 32-92 A: 0-60
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RTN ; Return | p: 93 A: 61
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ReceiveSync: P_LDH PB_RX_ON
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ReceiveSync: B_RST
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B_RC BMC_RX_CTRL
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WT BMC_CTRL_SIZE + 1
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P_LDH PB_RX_ON
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P_LDL PB_RSSI ; enable RSSI measurement
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WT 25
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WNT 1 ; Wait until beginning of slot |
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@ -260,7 +270,7 @@ ReceiveEnd: P_LDH PB_RSSI ; |
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Transmit: P_LDH 0x00 ;
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WT 40 ;
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B_RST ;
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B_RC TX_DESC ;
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B_RC BMC_TX_CTRL ;
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WNT 1 ; Wait until beginning of slot
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B_ST 0x00 ; Start transmission of S-field data |
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WT 1 ; Wait one bit | p: -8 S: 0
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@ -326,11 +336,8 @@ RFInit: RFEN ; Enable RF-clock
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MEN1
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WT 1
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RFInit2: P_LDL 0x20
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RFInit3: B_RST
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B_RC RX_DESC
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WT 8
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P_LDL 0x20
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WT 10
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MEN2
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WT 182
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MEN2N
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@ -390,8 +397,8 @@ InitDIP: B_RST
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BK_C BANK0_LOW
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C_LD DIP_CC_INIT
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WT 10
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B_RC DIP_RF_INIT
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WT 8
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B_RC BMC_CTRL_INIT
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WT BMC_CTRL_SIZE + 1
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B_RST
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;C_ON
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WT 10
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@ -402,8 +409,8 @@ InitDIP: B_RST
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RFStart: BR SyncInit
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;-------------------------------------------------------------
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SHARED DIP_CC_INIT,DIP_RF_INIT
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SHARED RF_DESC,RX_DESC,TX_DESC,TRX_DESC_FN
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SHARED DIP_CC_INIT,RF_DESC
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SHARED BMC_CTRL_INIT,BMC_RX_CTRL,BMC_TX_CTRL,BMC_CTRL_MFR_OFF
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SHARED SD_RSSI_OFF,SD_CSUM_OFF,SD_PREAMBLE_OFF,SD_DATA_OFF
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SHARED SlotTable
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@ -15,51 +15,51 @@ const unsigned char sc1442x_firmware[] = {
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0x08, 0x02, 0x0f, 0xa0, 0x08, 0x02, 0x6d, 0x00,
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0x0f, 0xb0, 0x08, 0x02, 0x0f, 0xc0, 0x08, 0x02,
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0x0f, 0xd0, 0x08, 0x02, 0x6f, 0x00, 0x01, 0x02,
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0x02, 0xa6, 0x02, 0x5d, 0x2d, 0x0e, 0x02, 0x83,
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0x01, 0x51, 0x02, 0xa6, 0x02, 0x6f, 0x2d, 0x0e,
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0x02, 0x83, 0x01, 0x51, 0x02, 0xa6, 0x02, 0x5d,
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0x2d, 0x0e, 0x02, 0x81, 0x01, 0x58, 0x02, 0xbd,
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0x01, 0x2a, 0x02, 0xa6, 0x02, 0x5d, 0x3d, 0x0e,
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0x02, 0x9e, 0x09, 0x03, 0x2b, 0x00, 0x09, 0x06,
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0x02, 0x83, 0x39, 0x00, 0x09, 0x06, 0x01, 0x5a,
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0x02, 0xa6, 0x02, 0x86, 0x02, 0x95, 0x01, 0x53,
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0x02, 0xa6, 0x02, 0x86, 0x25, 0x0e, 0x02, 0x92,
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0x01, 0x54, 0x02, 0xbd, 0x01, 0x40, 0x02, 0xa6,
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0x02, 0x86, 0x35, 0x0e, 0x02, 0x9e, 0x09, 0x03,
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0x24, 0x00, 0x09, 0x0d, 0x20, 0x00, 0x02, 0x95,
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0x01, 0x5a, 0x39, 0x00, 0x09, 0x06, 0x20, 0x00,
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0xec, 0x50, 0x09, 0x05, 0x08, 0x01, 0x04, 0x00,
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0x39, 0x00, 0x09, 0x06, 0x20, 0x00, 0xec, 0x50,
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0x04, 0x00, 0xed, 0x40, 0xec, 0x01, 0x09, 0x19,
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0x02, 0xa8, 0x02, 0x5b, 0x2d, 0x0e, 0x02, 0x85,
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0x01, 0x4f, 0x02, 0xa8, 0x02, 0x6f, 0x2d, 0x0e,
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0x02, 0x85, 0x01, 0x4f, 0x02, 0xbd, 0x02, 0xa8,
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0x02, 0x5b, 0x2d, 0x0e, 0x02, 0x83, 0x01, 0x56,
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0x02, 0xa8, 0x02, 0x5b, 0x3d, 0x0e, 0x02, 0xa0,
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0x09, 0x03, 0x2b, 0x00, 0x09, 0x06, 0x02, 0x85,
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0x39, 0x00, 0x09, 0x06, 0x01, 0x58, 0x02, 0xa8,
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0x02, 0x88, 0x02, 0x97, 0x01, 0x51, 0x02, 0xbd,
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0x02, 0xa8, 0x02, 0x88, 0x25, 0x0e, 0x02, 0x94,
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0x01, 0x52, 0x02, 0xa8, 0x02, 0x88, 0x35, 0x0e,
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0x02, 0xa0, 0x09, 0x03, 0x24, 0x00, 0x09, 0x0d,
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0x20, 0x00, 0x02, 0x97, 0x01, 0x58, 0x39, 0x00,
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0x09, 0x06, 0x20, 0x00, 0xec, 0x50, 0x09, 0x05,
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0x08, 0x01, 0x04, 0x00, 0x39, 0x00, 0x09, 0x06,
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0x20, 0x00, 0xec, 0x50, 0x04, 0x00, 0x20, 0x00,
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0x33, 0x48, 0xed, 0x40, 0xec, 0x01, 0x09, 0x19,
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0x08, 0x01, 0x09, 0x08, 0x27, 0x00, 0xea, 0x20,
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0xed, 0x02, 0x09, 0x05, 0x29, 0x00, 0x2c, 0x00,
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0x09, 0x0c, 0xec, 0x02, 0x09, 0x20, 0xea, 0x00,
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0x3f, 0x06, 0x09, 0x3e, 0x04, 0x00, 0xed, 0x40,
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0xec, 0x01, 0x09, 0x19, 0x08, 0x01, 0x09, 0x08,
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0x27, 0x00, 0xea, 0x20, 0xed, 0x02, 0x09, 0x05,
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0x29, 0x00, 0x2c, 0x00, 0x09, 0x0c, 0xec, 0x02,
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0x09, 0x20, 0xea, 0x00, 0x3f, 0x06, 0x09, 0x3e,
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0x04, 0x00, 0x09, 0xf9, 0x09, 0x4f, 0xed, 0x01,
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0xec, 0x40, 0x01, 0xc5, 0xed, 0x00, 0x09, 0x28,
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0x20, 0x00, 0x33, 0x40, 0x08, 0x01, 0x31, 0x00,
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0x09, 0x01, 0xed, 0x10, 0x09, 0x25, 0x37, 0x06,
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0x09, 0x3e, 0x04, 0x00, 0x09, 0xf9, 0x09, 0x54,
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0x20, 0x00, 0xec, 0x10, 0x09, 0x08, 0xec, 0x00,
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0x01, 0xc5, 0x27, 0x00, 0x09, 0x0f, 0x26, 0x00,
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0x09, 0x3d, 0x04, 0x00, 0x09, 0x3d, 0x02, 0x99,
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0x02, 0x99, 0x02, 0x99, 0x09, 0x01, 0x27, 0x00,
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0x09, 0x0b, 0x04, 0x00, 0x0b, 0x00, 0x09, 0x02,
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0xa4, 0x00, 0xb9, 0x3a, 0x09, 0x19, 0xa9, 0x00,
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0xa5, 0x00, 0xa4, 0x00, 0xb9, 0x3d, 0x09, 0x0a,
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0xa9, 0x00, 0xa5, 0x00, 0x09, 0x01, 0xec, 0x20,
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0x20, 0x00, 0x33, 0x48, 0x09, 0x08, 0xa7, 0x00,
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0x3f, 0x06, 0x09, 0x3e, 0x04, 0x00, 0x20, 0x00,
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0x33, 0x48, 0xed, 0x40, 0xec, 0x01, 0x09, 0x19,
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0x08, 0x01, 0x09, 0x08, 0x27, 0x00, 0xea, 0x20,
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0xed, 0x02, 0x09, 0x05, 0x29, 0x00, 0x2c, 0x00,
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0x09, 0x0c, 0xec, 0x02, 0x09, 0x20, 0xea, 0x00,
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0x3f, 0x06, 0x09, 0x3e, 0x04, 0x00, 0x09, 0xf9,
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0x09, 0x4f, 0xed, 0x01, 0xec, 0x40, 0x01, 0xc5,
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0xed, 0x00, 0x09, 0x28, 0x20, 0x00, 0x33, 0x40,
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0x08, 0x01, 0x31, 0x00, 0x09, 0x01, 0xed, 0x10,
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0x09, 0x25, 0x37, 0x06, 0x09, 0x3e, 0x04, 0x00,
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0x09, 0xf9, 0x09, 0x54, 0x20, 0x00, 0xec, 0x10,
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0x09, 0x08, 0xec, 0x00, 0x01, 0xc5, 0x27, 0x00,
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0x09, 0x0f, 0x26, 0x00, 0x09, 0x3d, 0x04, 0x00,
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0x09, 0x3d, 0x02, 0x9b, 0x02, 0x9b, 0x02, 0x9b,
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0x09, 0x01, 0x27, 0x00, 0x09, 0x0b, 0x04, 0x00,
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0x0b, 0x00, 0x09, 0x02, 0xa4, 0x00, 0xb9, 0x3a,
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0x09, 0x19, 0xa9, 0x00, 0xa5, 0x00, 0xa4, 0x00,
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0xb9, 0x3d, 0x09, 0x0a, 0xa9, 0x00, 0xa5, 0x00,
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0x09, 0x01, 0xec, 0x20, 0x09, 0x0a, 0xa7, 0x00,
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0x09, 0xb6, 0xa6, 0x00, 0xed, 0x00, 0x09, 0x10,
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0x04, 0x00, 0x40, 0x00, 0x50, 0x50, 0x09, 0x10,
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0x50, 0x00, 0x44, 0x00, 0x09, 0x27, 0x44, 0x00,
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0x04, 0x00, 0x5f, 0x70, 0x09, 0x0b, 0x5f, 0x00,
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0x40, 0x00, 0x04, 0x00, 0x40, 0x00, 0x57, 0x70,
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0x09, 0x0b, 0x57, 0x00, 0x04, 0x00, 0x0f, 0x20,
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0x02, 0xa6, 0x09, 0xfa, 0xea, 0x20, 0xed, 0x42,
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0x02, 0xa8, 0x09, 0xfa, 0xea, 0x20, 0xed, 0x42,
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0x28, 0x00, 0x09, 0x40, 0x26, 0x00, 0x29, 0x00,
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0x08, 0x14, 0x03, 0xde, 0x20, 0x00, 0x6b, 0x00,
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0x08, 0x17, 0x01, 0xd0, 0x08, 0x17, 0xea, 0x00,
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@ -4,11 +4,11 @@
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extern const unsigned char sc1442x_firmware[509];
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#define DIP_CC_INIT 0x10
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#define DIP_RF_INIT 0x0
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#define RF_DESC 0x3A
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#define RX_DESC 0x48
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#define TX_DESC 0x40
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#define TRX_DESC_FN 0x6
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#define BMC_CTRL_INIT 0x0
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#define BMC_RX_CTRL 0x48
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#define BMC_TX_CTRL 0x40
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#define BMC_CTRL_MFR_OFF 0x6
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#define SD_RSSI_OFF 0x0
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#define SD_CSUM_OFF 0x1
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#define SD_PREAMBLE_OFF 0x1
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@ -53,13 +53,13 @@ extern const unsigned char sc1442x_firmware[509];
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#define PSC_EOPSM 0x10
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#define RX_P00 0x20
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#define RX_P00_Sync 0x25
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#define RX_P32U 0x2A
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#define RX_P32P 0x31
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#define RX_P32U_Enc 0x2F
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#define TX_P00 0x3C
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#define RX_P32U 0x2B
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#define RX_P32P 0x30
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#define RX_P32U_Enc 0x2A
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#define TX_P00 0x3B
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#define TX_P32U 0x40
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#define TX_P32P 0x47
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#define TX_P32U_Enc 0x45
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#define TX_P32P 0x45
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#define TX_P32U_Enc 0x3F
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#define DCS_IV 0x50
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#define DCS_CK 0x58
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#define DCS_STATE 0x70
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