clk: add highbank clock support
This adds real clock support to Calxeda Highbank SOC using the common clock infrastructure. Signed-off-by: Rob Herring <rob.herring@calxeda.com> [mturquette@linaro.org: fixed up invalid writes to const struct member] Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Rob Herring
Mike Turquette
parent
260b6aa03e
commit
8d4d9f5208
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@ -0,0 +1,17 @@
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Device Tree Clock bindings for Calxeda highbank platform
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be one of the following:
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"calxeda,hb-pll-clock" - for a PLL clock
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"calxeda,hb-a9periph-clock" - The A9 peripheral clock divided from the
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A9 clock.
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"calxeda,hb-a9bus-clock" - The A9 bus clock divided from the A9 clock.
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"calxeda,hb-emmc-clock" - Divided clock for MMC/SD controller.
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- reg : shall be the control register offset from SYSREGs base for the clock.
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- clocks : shall be the input parent clock phandle for the clock. This is
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either an oscillator or a pll output.
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- #clock-cells : from common clock binding; shall be set to 0.
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@ -352,6 +352,7 @@ config ARCH_HIGHBANK
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select ARM_TIMER_SP804
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select CACHE_L2X0
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select CLKDEV_LOOKUP
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select COMMON_CLK
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select CPU_V7
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select GENERIC_CLOCKEVENTS
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select HAVE_ARM_SCU
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@ -1,5 +1,5 @@
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/*
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* Copyright 2011 Calxeda, Inc.
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* Copyright 2011-2012 Calxeda, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -24,6 +24,7 @@
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compatible = "calxeda,highbank";
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#address-cells = <1>;
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#size-cells = <1>;
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clock-ranges;
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cpus {
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#address-cells = <1>;
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@ -33,24 +34,32 @@
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compatible = "arm,cortex-a9";
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reg = <0>;
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next-level-cache = <&L2>;
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clocks = <&a9pll>;
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clock-names = "cpu";
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};
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cpu@1 {
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compatible = "arm,cortex-a9";
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reg = <1>;
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next-level-cache = <&L2>;
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clocks = <&a9pll>;
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clock-names = "cpu";
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};
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cpu@2 {
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compatible = "arm,cortex-a9";
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reg = <2>;
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next-level-cache = <&L2>;
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clocks = <&a9pll>;
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clock-names = "cpu";
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};
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cpu@3 {
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compatible = "arm,cortex-a9";
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reg = <3>;
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next-level-cache = <&L2>;
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clocks = <&a9pll>;
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clock-names = "cpu";
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};
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};
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@ -75,12 +84,14 @@
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xfff10600 0x20>;
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interrupts = <1 13 0xf01>;
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clocks = <&a9periphclk>;
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};
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watchdog@fff10620 {
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compatible = "arm,cortex-a9-twd-wdt";
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reg = <0xfff10620 0x20>;
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interrupts = <1 14 0xf01>;
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clocks = <&a9periphclk>;
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};
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intc: interrupt-controller@fff11000 {
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@ -116,12 +127,15 @@
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compatible = "calxeda,hb-sdhci";
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reg = <0xffe0e000 0x1000>;
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interrupts = <0 90 4>;
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clocks = <&eclk>;
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};
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ipc@fff20000 {
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compatible = "arm,pl320", "arm,primecell";
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reg = <0xfff20000 0x1000>;
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interrupts = <0 7 4>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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gpioe: gpio@fff30000 {
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@ -130,6 +144,8 @@
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gpio-controller;
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reg = <0xfff30000 0x1000>;
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interrupts = <0 14 4>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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gpiof: gpio@fff31000 {
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@ -138,6 +154,8 @@
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gpio-controller;
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reg = <0xfff31000 0x1000>;
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interrupts = <0 15 4>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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gpiog: gpio@fff32000 {
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@ -146,6 +164,8 @@
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gpio-controller;
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reg = <0xfff32000 0x1000>;
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interrupts = <0 16 4>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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gpioh: gpio@fff33000 {
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@ -154,24 +174,32 @@
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gpio-controller;
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reg = <0xfff33000 0x1000>;
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interrupts = <0 17 4>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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timer {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0xfff34000 0x1000>;
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interrupts = <0 18 4>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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rtc@fff35000 {
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compatible = "arm,pl031", "arm,primecell";
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reg = <0xfff35000 0x1000>;
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interrupts = <0 19 4>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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serial@fff36000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xfff36000 0x1000>;
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interrupts = <0 20 4>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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smic@fff3a000 {
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@ -186,12 +214,73 @@
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sregs@fff3c000 {
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compatible = "calxeda,hb-sregs";
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reg = <0xfff3c000 0x1000>;
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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osc: oscillator {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <33333000>;
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};
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ddrpll: ddrpll {
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#clock-cells = <0>;
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compatible = "calxeda,hb-pll-clock";
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clocks = <&osc>;
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reg = <0x108>;
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};
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a9pll: a9pll {
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#clock-cells = <0>;
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compatible = "calxeda,hb-pll-clock";
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clocks = <&osc>;
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reg = <0x100>;
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};
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a9periphclk: a9periphclk {
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#clock-cells = <0>;
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compatible = "calxeda,hb-a9periph-clock";
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clocks = <&a9pll>;
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reg = <0x104>;
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};
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a9bclk: a9bclk {
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#clock-cells = <0>;
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compatible = "calxeda,hb-a9bus-clock";
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clocks = <&a9pll>;
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reg = <0x104>;
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};
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emmcpll: emmcpll {
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#clock-cells = <0>;
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compatible = "calxeda,hb-pll-clock";
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clocks = <&osc>;
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reg = <0x10C>;
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};
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eclk: eclk {
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#clock-cells = <0>;
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compatible = "calxeda,hb-emmc-clock";
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clocks = <&emmcpll>;
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reg = <0x114>;
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};
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pclk: pclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <150000000>;
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};
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};
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};
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dma@fff3d000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0xfff3d000 0x1000>;
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interrupts = <0 92 4>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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ethernet@fff50000 {
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@ -1,4 +1,4 @@
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obj-y := clock.o highbank.o system.o smc.o
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obj-y := highbank.o system.o smc.o
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plus_sec := $(call as-instr,.arch_extension sec,+sec)
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AFLAGS_smc.o :=-Wa,-march=armv7-a$(plus_sec)
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@ -1,62 +0,0 @@
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/*
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* Copyright 2011 Calxeda, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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struct clk {
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unsigned long rate;
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};
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int clk_enable(struct clk *clk)
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{
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return 0;
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}
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void clk_disable(struct clk *clk)
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{}
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unsigned long clk_get_rate(struct clk *clk)
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{
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return clk->rate;
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}
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long clk_round_rate(struct clk *clk, unsigned long rate)
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{
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return clk->rate;
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}
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int clk_set_rate(struct clk *clk, unsigned long rate)
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{
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return 0;
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}
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static struct clk eclk = { .rate = 200000000 };
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static struct clk pclk = { .rate = 150000000 };
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static struct clk_lookup lookups[] = {
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{ .clk = &pclk, .con_id = "apb_pclk", },
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{ .clk = &pclk, .dev_id = "sp804", },
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{ .clk = &eclk, .dev_id = "ffe0e000.sdhci", },
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{ .clk = &pclk, .dev_id = "fff36000.serial", },
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};
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void __init highbank_clocks_init(void)
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{
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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}
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@ -105,6 +105,11 @@ static void __init highbank_init_irq(void)
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#endif
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}
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static struct clk_lookup lookup = {
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.dev_id = "sp804",
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.con_id = NULL,
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};
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static void __init highbank_timer_init(void)
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{
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int irq;
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@ -122,6 +127,8 @@ static void __init highbank_timer_init(void)
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irq = irq_of_parse_and_map(np, 0);
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highbank_clocks_init();
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lookup.clk = of_clk_get(np, 0);
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clkdev_add(&lookup);
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sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1");
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sp804_clockevents_init(timer_base, irq, "timer0");
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@ -3,6 +3,7 @@ obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o
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obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed-rate.o clk-gate.o \
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clk-mux.o clk-divider.o clk-fixed-factor.o
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# SoCs specific
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obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
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obj-$(CONFIG_ARCH_MXS) += mxs/
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obj-$(CONFIG_PLAT_SPEAR) += spear/
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obj-$(CONFIG_ARCH_U300) += clk-u300.o
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@ -0,0 +1,346 @@
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/*
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* Copyright 2011-2012 Calxeda, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/of.h>
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extern void __iomem *sregs_base;
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#define HB_PLL_LOCK_500 0x20000000
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#define HB_PLL_LOCK 0x10000000
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#define HB_PLL_DIVF_SHIFT 20
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#define HB_PLL_DIVF_MASK 0x0ff00000
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#define HB_PLL_DIVQ_SHIFT 16
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#define HB_PLL_DIVQ_MASK 0x00070000
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#define HB_PLL_DIVR_SHIFT 8
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#define HB_PLL_DIVR_MASK 0x00001f00
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#define HB_PLL_RANGE_SHIFT 4
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#define HB_PLL_RANGE_MASK 0x00000070
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#define HB_PLL_BYPASS 0x00000008
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#define HB_PLL_RESET 0x00000004
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#define HB_PLL_EXT_BYPASS 0x00000002
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#define HB_PLL_EXT_ENA 0x00000001
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#define HB_PLL_VCO_MIN_FREQ 2133000000
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#define HB_PLL_MAX_FREQ HB_PLL_VCO_MIN_FREQ
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#define HB_PLL_MIN_FREQ (HB_PLL_VCO_MIN_FREQ / 64)
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#define HB_A9_BCLK_DIV_MASK 0x00000006
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#define HB_A9_BCLK_DIV_SHIFT 1
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#define HB_A9_PCLK_DIV 0x00000001
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struct hb_clk {
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struct clk_hw hw;
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void __iomem *reg;
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char *parent_name;
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};
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#define to_hb_clk(p) container_of(p, struct hb_clk, hw)
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static int clk_pll_prepare(struct clk_hw *hwclk)
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{
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struct hb_clk *hbclk = to_hb_clk(hwclk);
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u32 reg;
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reg = readl(hbclk->reg);
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reg &= ~HB_PLL_RESET;
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writel(reg, hbclk->reg);
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while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
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;
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while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)
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;
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return 0;
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}
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static void clk_pll_unprepare(struct clk_hw *hwclk)
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{
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struct hb_clk *hbclk = to_hb_clk(hwclk);
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u32 reg;
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reg = readl(hbclk->reg);
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reg |= HB_PLL_RESET;
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writel(reg, hbclk->reg);
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}
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static int clk_pll_enable(struct clk_hw *hwclk)
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{
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struct hb_clk *hbclk = to_hb_clk(hwclk);
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u32 reg;
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reg = readl(hbclk->reg);
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reg |= HB_PLL_EXT_ENA;
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writel(reg, hbclk->reg);
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return 0;
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}
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static void clk_pll_disable(struct clk_hw *hwclk)
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{
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struct hb_clk *hbclk = to_hb_clk(hwclk);
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u32 reg;
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reg = readl(hbclk->reg);
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reg &= ~HB_PLL_EXT_ENA;
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writel(reg, hbclk->reg);
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}
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static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
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unsigned long parent_rate)
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{
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struct hb_clk *hbclk = to_hb_clk(hwclk);
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unsigned long divf, divq, vco_freq, reg;
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reg = readl(hbclk->reg);
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if (reg & HB_PLL_EXT_BYPASS)
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return parent_rate;
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divf = (reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT;
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divq = (reg & HB_PLL_DIVQ_MASK) >> HB_PLL_DIVQ_SHIFT;
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vco_freq = parent_rate * (divf + 1);
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return vco_freq / (1 << divq);
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}
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static void clk_pll_calc(unsigned long rate, unsigned long ref_freq,
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u32 *pdivq, u32 *pdivf)
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{
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u32 divq, divf;
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unsigned long vco_freq;
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if (rate < HB_PLL_MIN_FREQ)
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rate = HB_PLL_MIN_FREQ;
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if (rate > HB_PLL_MAX_FREQ)
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rate = HB_PLL_MAX_FREQ;
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for (divq = 1; divq <= 6; divq++) {
|
||||
if ((rate * (1 << divq)) >= HB_PLL_VCO_MIN_FREQ)
|
||||
break;
|
||||
}
|
||||
|
||||
vco_freq = rate * (1 << divq);
|
||||
divf = (vco_freq + (ref_freq / 2)) / ref_freq;
|
||||
divf--;
|
||||
|
||||
*pdivq = divq;
|
||||
*pdivf = divf;
|
||||
}
|
||||
|
||||
static long clk_pll_round_rate(struct clk_hw *hwclk, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
u32 divq, divf;
|
||||
unsigned long ref_freq = *parent_rate;
|
||||
|
||||
clk_pll_calc(rate, ref_freq, &divq, &divf);
|
||||
|
||||
return (ref_freq * (divf + 1)) / (1 << divq);
|
||||
}
|
||||
|
||||
static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct hb_clk *hbclk = to_hb_clk(hwclk);
|
||||
u32 divq, divf;
|
||||
u32 reg;
|
||||
|
||||
clk_pll_calc(rate, parent_rate, &divq, &divf);
|
||||
|
||||
reg = readl(hbclk->reg);
|
||||
if (divf != ((reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT)) {
|
||||
/* Need to re-lock PLL, so put it into bypass mode */
|
||||
reg |= HB_PLL_EXT_BYPASS;
|
||||
writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
|
||||
|
||||
writel(reg | HB_PLL_RESET, hbclk->reg);
|
||||
reg &= ~(HB_PLL_DIVF_MASK | HB_PLL_DIVQ_MASK);
|
||||
reg |= (divf << HB_PLL_DIVF_SHIFT) | (divq << HB_PLL_DIVQ_SHIFT);
|
||||
writel(reg | HB_PLL_RESET, hbclk->reg);
|
||||
writel(reg, hbclk->reg);
|
||||
|
||||
while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
|
||||
;
|
||||
while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)
|
||||
;
|
||||
reg |= HB_PLL_EXT_ENA;
|
||||
reg &= ~HB_PLL_EXT_BYPASS;
|
||||
} else {
|
||||
reg &= ~HB_PLL_DIVQ_MASK;
|
||||
reg |= divq << HB_PLL_DIVQ_SHIFT;
|
||||
}
|
||||
writel(reg, hbclk->reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clk_ops clk_pll_ops = {
|
||||
.prepare = clk_pll_prepare,
|
||||
.unprepare = clk_pll_unprepare,
|
||||
.enable = clk_pll_enable,
|
||||
.disable = clk_pll_disable,
|
||||
.recalc_rate = clk_pll_recalc_rate,
|
||||
.round_rate = clk_pll_round_rate,
|
||||
.set_rate = clk_pll_set_rate,
|
||||
};
|
||||
|
||||
static unsigned long clk_cpu_periphclk_recalc_rate(struct clk_hw *hwclk,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct hb_clk *hbclk = to_hb_clk(hwclk);
|
||||
u32 div = (readl(hbclk->reg) & HB_A9_PCLK_DIV) ? 8 : 4;
|
||||
return parent_rate / div;
|
||||
}
|
||||
|
||||
static const struct clk_ops a9periphclk_ops = {
|
||||
.recalc_rate = clk_cpu_periphclk_recalc_rate,
|
||||
};
|
||||
|
||||
static unsigned long clk_cpu_a9bclk_recalc_rate(struct clk_hw *hwclk,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct hb_clk *hbclk = to_hb_clk(hwclk);
|
||||
u32 div = (readl(hbclk->reg) & HB_A9_BCLK_DIV_MASK) >> HB_A9_BCLK_DIV_SHIFT;
|
||||
|
||||
return parent_rate / (div + 2);
|
||||
}
|
||||
|
||||
static const struct clk_ops a9bclk_ops = {
|
||||
.recalc_rate = clk_cpu_a9bclk_recalc_rate,
|
||||
};
|
||||
|
||||
static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct hb_clk *hbclk = to_hb_clk(hwclk);
|
||||
u32 div;
|
||||
|
||||
div = readl(hbclk->reg) & 0x1f;
|
||||
div++;
|
||||
div *= 2;
|
||||
|
||||
return parent_rate / div;
|
||||
}
|
||||
|
||||
static long clk_periclk_round_rate(struct clk_hw *hwclk, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
u32 div;
|
||||
|
||||
div = *parent_rate / rate;
|
||||
div++;
|
||||
div &= ~0x1;
|
||||
|
||||
return *parent_rate / div;
|
||||
}
|
||||
|
||||
static int clk_periclk_set_rate(struct clk_hw *hwclk, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct hb_clk *hbclk = to_hb_clk(hwclk);
|
||||
u32 div;
|
||||
|
||||
div = parent_rate / rate;
|
||||
if (div & 0x1)
|
||||
return -EINVAL;
|
||||
|
||||
writel(div >> 1, hbclk->reg);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clk_ops periclk_ops = {
|
||||
.recalc_rate = clk_periclk_recalc_rate,
|
||||
.round_rate = clk_periclk_round_rate,
|
||||
.set_rate = clk_periclk_set_rate,
|
||||
};
|
||||
|
||||
static __init struct clk *hb_clk_init(struct device_node *node, const struct clk_ops *ops)
|
||||
{
|
||||
u32 reg;
|
||||
struct clk *clk;
|
||||
struct hb_clk *hb_clk;
|
||||
const char *clk_name = node->name;
|
||||
const char *parent_name;
|
||||
struct clk_init_data init;
|
||||
int rc;
|
||||
|
||||
rc = of_property_read_u32(node, "reg", ®);
|
||||
if (WARN_ON(rc))
|
||||
return NULL;
|
||||
|
||||
hb_clk = kzalloc(sizeof(*hb_clk), GFP_KERNEL);
|
||||
if (WARN_ON(!hb_clk))
|
||||
return NULL;
|
||||
|
||||
hb_clk->reg = sregs_base + reg;
|
||||
|
||||
of_property_read_string(node, "clock-output-names", &clk_name);
|
||||
|
||||
init.name = clk_name;
|
||||
init.ops = ops;
|
||||
init.flags = 0;
|
||||
parent_name = of_clk_get_parent_name(node, 0);
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
|
||||
hb_clk->hw.init = &init;
|
||||
|
||||
clk = clk_register(NULL, &hb_clk->hw);
|
||||
if (WARN_ON(IS_ERR(clk))) {
|
||||
kfree(hb_clk);
|
||||
return NULL;
|
||||
}
|
||||
rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
return clk;
|
||||
}
|
||||
|
||||
static void __init hb_pll_init(struct device_node *node)
|
||||
{
|
||||
hb_clk_init(node, &clk_pll_ops);
|
||||
}
|
||||
|
||||
static void __init hb_a9periph_init(struct device_node *node)
|
||||
{
|
||||
hb_clk_init(node, &a9periphclk_ops);
|
||||
}
|
||||
|
||||
static void __init hb_a9bus_init(struct device_node *node)
|
||||
{
|
||||
struct clk *clk = hb_clk_init(node, &a9bclk_ops);
|
||||
clk_prepare_enable(clk);
|
||||
}
|
||||
|
||||
static void __init hb_emmc_init(struct device_node *node)
|
||||
{
|
||||
hb_clk_init(node, &periclk_ops);
|
||||
}
|
||||
|
||||
static const __initconst struct of_device_id clk_match[] = {
|
||||
{ .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
|
||||
{ .compatible = "calxeda,hb-pll-clock", .data = hb_pll_init, },
|
||||
{ .compatible = "calxeda,hb-a9periph-clock", .data = hb_a9periph_init, },
|
||||
{ .compatible = "calxeda,hb-a9bus-clock", .data = hb_a9bus_init, },
|
||||
{ .compatible = "calxeda,hb-emmc-clock", .data = hb_emmc_init, },
|
||||
{}
|
||||
};
|
||||
|
||||
void __init highbank_clocks_init(void)
|
||||
{
|
||||
of_clk_init(clk_match);
|
||||
}
|
||||
Reference in New Issue