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Some OMAP PRCM and sparse fixes against v3.8-rc1. A basic set of test 

logs are available here:
 
     http://www.pwsan.com/omap/testlogs/prcm_fixes_b_3.8-rc/20130102120724/
 
 The 3730 Beagle XM here has an intermittent failure mounting SD root,
 but the suspicion right now is that this is due to a failing SD card,
 rather than any change introduced by these patches.
 
 This second version includes a few changes requested by Tony Lindgren.
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Merge tag 'omap-fixes-a2-for-v3.8-rc' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.8-rc2/fixes

Some OMAP PRCM and sparse fixes against v3.8-rc1.  A basic set of test
logs are available here:

    http://www.pwsan.com/omap/testlogs/prcm_fixes_b_3.8-rc/20130102120724/

The 3730 Beagle XM here has an intermittent failure mounting SD root,
but the suspicion right now is that this is due to a failing SD card,
rather than any change introduced by these patches.

This second version includes a few changes requested by Tony Lindgren.
This commit is contained in:
Tony Lindgren 2013-01-03 11:04:21 -08:00
parent d1c3ed669a 7e7fff8254
commit 2cd1f483b8
9 changed files with 123 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/mach-omap2/cclock3xxx_data.c
View File

@ -1167,6 +1167,8 @@ static const struct clk_ops emu_src_ck_ops = {
.recalc_rate = &omap2_clksel_recalc,
.get_parent = &omap2_clksel_find_parent_index,
.set_parent = &omap2_clksel_set_parent,
.enable = &omap2_clkops_enable_clkdm,
.disable = &omap2_clkops_disable_clkdm,
};
static struct clk emu_src_ck;

4
arch/arm/mach-omap2/omap_hwmod_33xx_data.c
View File

@ -2515,7 +2515,7 @@ static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
.user = OCP_USER_MPU,
};
struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
static struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
{
.pa_start = 0x4A101000,
.pa_end = 0x4A101000 + SZ_256 - 1,
@ -2523,7 +2523,7 @@ struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
{ }
};
struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
.master = &am33xx_cpgmac0_hwmod,
.slave = &am33xx_mdio_hwmod,
.addr = am33xx_mdio_addr_space,

88
arch/arm/mach-omap2/prm2xxx.c
View File

@ -27,6 +27,14 @@
#include "cm2xxx_3xxx.h"
#include "prm-regbits-24xx.h"
/*
* OMAP24xx PM_PWSTCTRL_*.POWERSTATE and PM_PWSTST_*.LASTSTATEENTERED bits -
* these are reversed from the bits used on OMAP3+
*/
#define OMAP24XX_PWRDM_POWER_ON 0x0
#define OMAP24XX_PWRDM_POWER_RET 0x1
#define OMAP24XX_PWRDM_POWER_OFF 0x3
/*
* omap2xxx_prm_reset_src_map - map from bits in the PRM_RSTST_WKUP
* hardware register (which are specific to the OMAP2xxx SoCs) to
@ -67,6 +75,34 @@ static u32 omap2xxx_prm_read_reset_sources(void)
return r;
}
/**
* omap2xxx_pwrst_to_common_pwrst - convert OMAP2xxx pwrst to common pwrst
* @omap2xxx_pwrst: OMAP2xxx hardware power state to convert
*
* Return the common power state bits corresponding to the OMAP2xxx
* hardware power state bits @omap2xxx_pwrst, or -EINVAL upon error.
*/
static int omap2xxx_pwrst_to_common_pwrst(u8 omap2xxx_pwrst)
{
u8 pwrst;
switch (omap2xxx_pwrst) {
case OMAP24XX_PWRDM_POWER_OFF:
pwrst = PWRDM_POWER_OFF;
break;
case OMAP24XX_PWRDM_POWER_RET:
pwrst = PWRDM_POWER_RET;
break;
case OMAP24XX_PWRDM_POWER_ON:
pwrst = PWRDM_POWER_ON;
break;
default:
return -EINVAL;
}
return pwrst;
}
/**
* omap2xxx_prm_dpll_reset - use DPLL reset to reboot the OMAP SoC
*
@ -97,10 +133,56 @@ int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm)
return 0;
}
static int omap2xxx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
{
u8 omap24xx_pwrst;
switch (pwrst) {
case PWRDM_POWER_OFF:
omap24xx_pwrst = OMAP24XX_PWRDM_POWER_OFF;
break;
case PWRDM_POWER_RET:
omap24xx_pwrst = OMAP24XX_PWRDM_POWER_RET;
break;
case PWRDM_POWER_ON:
omap24xx_pwrst = OMAP24XX_PWRDM_POWER_ON;
break;
default:
return -EINVAL;
}
omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
(omap24xx_pwrst << OMAP_POWERSTATE_SHIFT),
pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
return 0;
}
static int omap2xxx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
{
u8 omap2xxx_pwrst;
omap2xxx_pwrst = omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
OMAP2_PM_PWSTCTRL,
OMAP_POWERSTATE_MASK);
return omap2xxx_pwrst_to_common_pwrst(omap2xxx_pwrst);
}
static int omap2xxx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
{
u8 omap2xxx_pwrst;
omap2xxx_pwrst = omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
OMAP2_PM_PWSTST,
OMAP_POWERSTATEST_MASK);
return omap2xxx_pwrst_to_common_pwrst(omap2xxx_pwrst);
}
struct pwrdm_ops omap2_pwrdm_operations = {
.pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst,
.pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst,
.pwrdm_read_pwrst = omap2_pwrdm_read_pwrst,
.pwrdm_set_next_pwrst = omap2xxx_pwrdm_set_next_pwrst,
.pwrdm_read_next_pwrst = omap2xxx_pwrdm_read_next_pwrst,
.pwrdm_read_pwrst = omap2xxx_pwrdm_read_pwrst,
.pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst,
.pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst,
.pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst,

22
arch/arm/mach-omap2/prm2xxx_3xxx.c
View File

@ -103,28 +103,6 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift)
/* Powerdomain low-level functions */
/* Common functions across OMAP2 and OMAP3 */
int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
{
omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
(pwrst << OMAP_POWERSTATE_SHIFT),
pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
return 0;
}
int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
{
return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
OMAP2_PM_PWSTCTRL,
OMAP_POWERSTATE_MASK);
}
int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm)
{
return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
OMAP2_PM_PWSTST,
OMAP_POWERSTATEST_MASK);
}
int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
u8 pwrst)
{

28
arch/arm/mach-omap2/prm3xxx.c
View File

@ -277,6 +277,28 @@ static u32 omap3xxx_prm_read_reset_sources(void)
/* Powerdomain low-level functions */
static int omap3_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
{
omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
(pwrst << OMAP_POWERSTATE_SHIFT),
pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
return 0;
}
static int omap3_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
{
return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
OMAP2_PM_PWSTCTRL,
OMAP_POWERSTATE_MASK);
}
static int omap3_pwrdm_read_pwrst(struct powerdomain *pwrdm)
{
return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
OMAP2_PM_PWSTST,
OMAP_POWERSTATEST_MASK);
}
/* Applicable only for OMAP3. Not supported on OMAP2 */
static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
{
@ -355,9 +377,9 @@ static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
}
struct pwrdm_ops omap3_pwrdm_operations = {
.pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst,
.pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst,
.pwrdm_read_pwrst = omap2_pwrdm_read_pwrst,
.pwrdm_set_next_pwrst = omap3_pwrdm_set_next_pwrst,
.pwrdm_read_next_pwrst = omap3_pwrdm_read_next_pwrst,
.pwrdm_read_pwrst = omap3_pwrdm_read_pwrst,
.pwrdm_read_prev_pwrst = omap3_pwrdm_read_prev_pwrst,
.pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst,
.pwrdm_read_logic_pwrst = omap3_pwrdm_read_logic_pwrst,

6
arch/arm/mach-omap2/prm44xx.c
View File

@ -56,9 +56,9 @@ static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
* enumeration)
*/
static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = {
{ OMAP4430_RST_GLOBAL_WARM_SW_SHIFT,
{ OMAP4430_GLOBAL_WARM_SW_RST_SHIFT,
OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT },
{ OMAP4430_RST_GLOBAL_COLD_SW_SHIFT,
{ OMAP4430_GLOBAL_COLD_RST_SHIFT,
OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT },
{ OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT,
OMAP_SECU_VIOL_RST_SRC_ID_SHIFT },
@ -333,7 +333,7 @@ static u32 omap44xx_prm_read_reset_sources(void)
u32 r = 0;
u32 v;
v = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
OMAP4_RM_RSTST);
p = omap44xx_prm_reset_src_map;

4
arch/arm/mach-omap2/prm44xx.h
View File

@ -62,8 +62,8 @@
/* OMAP4 specific register offsets */
#define OMAP4_RM_RSTCTRL 0x0000
#define OMAP4_RM_RSTTIME 0x0004
#define OMAP4_RM_RSTST 0x0008
#define OMAP4_RM_RSTST 0x0004
#define OMAP4_RM_RSTTIME 0x0008
#define OMAP4_PM_PWSTCTRL 0x0000
#define OMAP4_PM_PWSTST 0x0004

2
arch/arm/plat-omap/counter_32k.c
View File

@ -22,6 +22,8 @@
#include <asm/mach/time.h>
#include <asm/sched_clock.h>
#include <plat/counter-32k.h>
/* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
#define OMAP2_32KSYNCNT_REV_OFF 0x0
#define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30)

2
arch/arm/plat-omap/sram.c
View File

@ -26,6 +26,8 @@
#include <asm/mach/map.h>
#include <plat/sram.h>
#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
static void __iomem *omap_sram_base;